Electrostatic protection circuit

Patent metadata

Field	Value
Publication number	US-10468870-B2
Application number	US-201816015424-A
Country	US
Kind code	B2
Filing date	Jun 22, 2018
Priority date	Mar 2, 2015
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

An electrostatic protection circuit includes a trigger circuit that is connected between a first power line and a second power line. The trigger circuit is configured to output a trigger signal in response to a voltage fluctuation between the first and second power lines. A shunt element has a main current path between the first power line and the second power line and is controllable to be on and off using the trigger signal. A control circuit is configured to supply a control signal to turn off the shunt element when a current value of the main current path of the shunt element exceeds a predetermined threshold value.

First claim

What is claimed is:

1. An electrostatic protection circuit, comprising:
a trigger circuit connected between a first power line and a second power line and configured to output a trigger signal in response to a voltage fluctuation on the first and second power lines;
a shunt element connected between the first power line and the second power line and configured to be turned on and off according to the trigger signal; and
a control circuit configured to supply a control signal causing the shunt element to turn off when a current level flowing through the shunt element exceeds a predetermined threshold value.

2. The electrostatic protection circuit according to claim 1 , wherein the control circuit includes:
a resistor connected in series with a main current path of the shunt element between the first and second power lines, and
a transistor having a gate connected to a node between the resistor and the shunt element and a source connected to one of the first and second power lines.

3. The electrostatic protection circuit according to claim 1 , further comprising:
a buffer circuit connected between the trigger circuit and the shunt element, wherein
the trigger signal is supplied to the shunt element through the buffer circuit.

4. The electrostatic protection circuit according to claim 1 , wherein the control circuit includes:
a first resistor connected in series with a main current path of the shunt element between the first and second power lines, and
a first transistor having a gate connected to a connection node between the first resistor and the shunt element and a source connected to a one of the first and second power lines; and
the control signal is supplied to a gate of a second transistor, the second transistor having a main current path connected between a control electrode of the shunt element and one of the first and second power lines, the control signal causing the second transistor to connect the control electrode to the one of the first and second power lines to cause the shunt element to turn off.

5. The electrostatic protection circuit according to claim 1 , wherein
the shunt element is a first n-channel transistor;
the control circuit includes:
a first resistor connected between the first power line and a drain of the first n-channel transistor, and
a p-channel transistor having a gate connected to a connection node between the shunt element and the first resistor, a source connected to the first power line, and a drain connected to a second resistor that is connected to the second power line; and

a node between the p-channel transistor and the second resistor is connected to a gate of a second n-channel transistor that has a drain connected to a gate of the first n-channel transistor and a source connected to the second power line.

6. The electrostatic protection circuit according to claim 5 , further comprising:
a first inverter and a second inverter connected in series between the trigger circuit and the gate of the first n-channel transistor, wherein the trigger signal is supplied to the gate of the first n-channel transistor through the first and second inverters.

7. The electrostatic protection circuit according to claim 1 , wherein
the shunt element is a first p-channel transistor;
the control circuit includes:
a first resistor connected between the second power line and a drain of the first p-channel transistor, and
a n-channel transistor having a gate connected to a connection node between the shunt element and the first resistor, a source connected to the second power line, and a drain connected to a second resistor that is connected to the first power line; and

a node between the n-channel transistor and the second resistor is connected to a gate of a second p-channel transistor that has a drain connected to a gate of the first n-channel transistor and a source connected to the first power line.

8. The electrostatic protection circuit according to claim 7 , further comprising:
a first inverter and a second inverter connected in series between the trigger circuit and the gate of the first p-channel transistor, wherein the trigger signal is supplied to the gate of the first p-channel transistor through the first and second inverters.

9. The electrostatic protection circuit according to claim 1 , wherein the trigger circuit comprises a capacitor and a resistor connected in series between the first and second power lines.

10. The electrostatic protection circuit according to claim 9 , wherein the capacitor is connected to the first power line and the resistor is connected to the second power line.

11. The electrostatic protection circuit according to claim 1 , wherein the shunt element is a bipolar transistor.

12. The electrostatic protection circuit according to claim 1 , wherein the shunt element is a double-diffused metal-oxide-semiconductor transistor.

13. An electrostatic protection circuit, comprising:
a trigger circuit including a capacitor and a first resistor connected in series between a first power line and a second power line;
a first transistor connected between the first power line and the second power line and connected to a connection node between the capacitor and the first resistor;
a second resistor connected in series with a current path of the first transistor between the first and second power lines;
a second transistor directly connected to a connection node between the second resistor and the first transistor and having a current path connected between the first and second power lines;
a third resistor connected in series with the current path of the second transistor between the first and second power lines; and
a third transistor directly connected to a connection node between the third resistor and the second transistor having and a current path connected between the first transistor and one of the first and second power lines.

14. The electrostatic protection circuit according to claim 13 , further comprising:
a buffer circuit connected between the first transistor and the connection node between the first resistor and the capacitor.

15. The electrostatic protection circuit according to claim 13 , wherein
the first transistor is a NMOS transistor,
the second transistor is a PMOS transistor,
the third transistor is a NMOS transistor.

16. The electrostatic protection circuit according to claim 13 , wherein
the first transistor is a PMOS transistor,
the second transistor is a NMOS transistor,
the third transistor is a PMOS transistor.

Assignees

• Toshiba Kk

Inventors

• Kato Kazuhiro

Classifications

• H02H9/042

  comprising means to limit the absorbed power or indicate damaged over-voltage protection device · CPC title

• H02H7/008

  for protective arrangements according to this subclass (H02H9/042, H02H9/043 take precedence; protection of spark-gaps H02H7/24) · CPC title

• H02H3/20 Primary

  responsive to excess voltage · CPC title

• H02H9/041 Primary

  using a short-circuiting device · CPC title

• H10D89/811

  using FETs as protective elements · CPC title