Electro static discharge clamping device

Patent metadata

Field	Value
Publication number	US-9728512-B2
Application number	US-201113158708-A
Country	US
Kind code	B2
Filing date	Jun 13, 2011
Priority date	Dec 5, 2008
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

Electrostatic discharge clamp devices are described. In one embodiment, the semiconductor device includes a first transistor, the first transistor including a first source/drain and a second source/drain, the first source/drain coupled to a first potential node, the second source/drain coupled to a second potential node. The device further includes a OR logic block, a first input of the OR logic block coupled to the first potential node through a capacitor, the first input of the OR logic block being coupled to the second potential node through a resistor, and a second input of the OR logic block coupled to a substrate pickup node of the first transistor.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first well region disposed in a substrate, the first well region comprising a first doping type;
a first source/drain region disposed in the first well region, the first source/drain region being coupled to a first potential node;
a second source/drain region disposed in the first well region, the first and the second source/drain regions comprising a second doping type, the second doping type being opposite to the first doping type, the second source/drain region being coupled to a second potential node;
an OR logic block;
a first gate electrode disposed above the substrate, the first gate electrode disposed between the first and the second source/drain regions, the first gate electrode coupled to an output of the OR logic block;
a pickup region disposed in the first well region, the pickup region comprising the first doping type, the pickup region coupled to an input of the OR logic block; and
a body contact region comprising the first doping type and disposed in the first well region, the body contact region being coupled to the second potential node, wherein the body contact region is coupled to a body region of a transistor through a substrate resistor, wherein the pickup region is coupled to the body region of the transistor without the substrate resistor, the transistor comprising the first source/drain region and the second source/drain region, wherein the body contact region is coupled to a first portion of the first well region adjacent the first source/drain region through the substrate resistor, the substrate resistor comprising a second portion of the first well region and a portion of the substrate.

2. The device of claim 1 , wherein the substrate comprises a doped substrate.

3. The device of claim 1 , wherein the OR logic block comprises an OR gate.

4. The device of claim 1 , wherein the OR logic block comprises a NOR gate coupled to a first inverting buffer, wherein the input of the OR logic block is a first input of the NOR gate, and wherein a second input of the OR logic block is a second input of the NOR gate, and wherein an output of the NOR gate is coupled to an input of the first inverting buffer.

5. The device of claim 4 , wherein the NOR gate comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, wherein a first source/drain of the first PMOS transistor is coupled to the first potential node, wherein a second source/drain of the first PMOS transistor is coupled to the first source/drain of the second PMOS transistor, and wherein a second source/drain of the second PMOS transistor is coupled to a first source/drain of the first NMOS transistor, wherein a second source/drain of the first NMOS transistor is coupled to the second potential node, wherein a first source/drain of the second NMOS transistor is coupled to the second source/drain of the PMOS transistor, wherein a second source/drain of the second NMOS transistor is coupled to the second potential node.

6. The device of claim 5 , wherein the first input of the NOR gate is coupled to a gate of the first PMOS and NMOS transistors, and wherein the second input of the NOR gate is coupled to the gate of the second PMOS and NMOS transistors.

7. The device of claim 5 , wherein the second source/drain of the second PMOS transistor, and the first source/drain of the first and the second NMOS transistors are coupled to the output node of the NOR gate.

8. The device of claim 4 , wherein the first inverting buffer comprises a CMOS inverter, the input of the CMOS inverter being coupled to the output of the NOR gate, the output of the CMOS inverter being coupled to the first gate electrode.

9. The device of claim 1 , further comprising a shielding region laterally shielding the body contact region from the pickup region.

10. The device of claim 1 , wherein the first doping type comprises a p type doping, and the second doping type comprises an n type doping.

11. The device of claim 1 , wherein the first potential node comprises a power supply node, and wherein the second potential node comprises a ground potential node.

12. A semiconductor device comprising:
a first well region disposed in a substrate, the first well region comprising a first doping type;
a second well region disposed under the first well region, the second well region comprising a second doping type;
a first source/drain region of a transistor disposed in the first well region, the first source/drain region being coupled to a first potential node;
a second source/drain region of the transistor disposed in the first well region, the first and the second source/drain regions comprising the second doping type, the second doping type being opposite to the first doping type, the second source/drain region being coupled to a second potential node;
an OR logic block;
a first gate electrode of the transistor disposed above the substrate, the first gate electrode disposed between the first and the second source/drain regions, the first gate electrode coupled to an output of the OR logic block;
a pickup region of the transistor disposed in the first well region, the pickup region comprising the first doping type, the pickup region coupled to an input of the OR logic block; and
a body contact region of the transistor comprising the first doping type and disposed in the first well region, the body contact region being coupled to the second potential node, wherein the pickup region is coupled to a body region of the transistor through the first well region, wherein the transistor comprises the first source/drain region and the second source/drain region separated by the body region, wherein the second well region vertically shields the body contact region from the pickup region.

13. A semiconductor device comprising:
a first well region disposed in a substrate, the first well region comprising a first doping type;
a first source/drain region disposed in the first well region, the first source/drain region being coupled to a first potential node;
a second source/drain region disposed in the first well region, the first and the second source/drain regions comprising a second doping type, the second doping type being opposite to the first doping type, the second source/drain region being coupled to a second potential node;
a body region disposed in the first well region under the first and the second source/drain regions;
a concentric shaped body contact region of the first doping type disposed in the first well region, the body contact region surrounding the first and the second source/drain regions, wherein the body contact region is coupled to the body region and to the second potential node;
an OR logic block;
a first gate electrode disposed above the substrate, the first gate electrode disposed between the first and the second source/drain regions, the first gate electrode coupled to an output of the OR logic block; and
a pickup region disposed in the first well region and coupled to the body region, the pickup region coupled to an input of the OR logic block, wherein the pickup region and the body contact region are separated by a substrate resistor that is disposed outside the first well region.

14. The device of claim 13 , further comprising a concentric shaped shield region of a second doping type disposed in the first well region, the shield region disposed between the body contact region and the first and the second source/drain regions.

15. The device of claim 13 , wherein the OR logic block comprises a NOR gate coupled to a first inverting buffer, wherein

Assignees

• Russ Cornelius Christian
• Infineon Technologies Ag

Inventors

• Russ Cornelius Christian

Classifications

• H10W42/60 Primary

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H01L27/0285

  Electricity · mapped topic

• H01L23/60 Primary

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic