Integrated enhancement mode and depletion mode device structure and method of making the same

Patent metadata

Field	Value
Publication number	US-10468406-B2
Application number	US-201414509750-A
Country	US
Kind code	B2
Filing date	Oct 8, 2014
Priority date	Oct 8, 2014
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A circuit is provided that includes a castellated channel device that comprises a heterostructure overlying a substrate structure, a castellated channel device area formed in the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, and a three-sided castellated conductive gate contact that extends across the castellated channel device area. The three-sided gate contact substantially surrounds each ridge channel around their tops and their sides to overlap a channel interface of heterostructure of each of the plurality of ridge channels. The three-sided castellated conductive gate contact extends along at least a portion of a length of each ridge channel.

First claim

What is claimed is:

1. A circuit comprising:
a castellated channel device comprising:
a heterostructure overlying an underlying structure, the underlying structure comprising a given semiconducting material;
a castellated channel device area formed in the heterostructure that defines a plurality of ridge channels comprising another semiconducting material formed over the underlying structure, the plurality of ridge channels being interleaved between a plurality of trenches, wherein a top planar semiconductor surface of the given semiconductor material in the underlying structure between ridge channels is exposed in each of the plurality of trenches; and
a three-sided castellated conductive gate contact that extends across the castellated channel device area and substantially surrounds each ridge channel around its top and its sides to overlap a channel interface of each of the plurality of ridge channels, the three-sided castellated conductive gate contact extending along at least a portion of a length of each ridge channel;
a planar channel device formed from a first portion of a single shared heterostructure overlying the underlying structure in a planar channel device area, and having a planar gate contact that is in contact with the first portion of the single shared heterostructure, wherein the single shared heterostructure forms the heterostructure of the castellated channel device; and
an isolation region in the single shared heterostructure that electrically isolates the planar channel device from the castellated channel device.

2. The circuit of claim 1 , wherein the single shared heterostructure comprises an aluminum gallium nitride (AlGaN) layer overlying a gallium nitride layer (GaN).

3. The circuit of claim 1 , wherein the planar channel device is a d-mode device and the castellated channel device is an e-mode device.

4. An integrated circuit comprising:
a planar channel device comprising a first portion of a single shared heterostructure overlying an underlying structure in a planar channel device area, and having a planar gate contact that is in contact with the first portion of the single shared heterostructure, wherein the underlying structure is formed of a given semiconducting material; and
a castellated channel device comprising a second portion of the single shared heterostructure overlying the underlying structure in a castellated channel device area, and having a castellated gate contact that extends to contact a top surface of the underlying structure and substantially surrounds a channel interface of each ridge channel of a castellated channel in the castellated channel device area, wherein each ridge channel is formed of another semiconducting material, the castellated channel device area also having a plurality of trenches, wherein each trench exposes a top planar semiconductor surface of the given semiconductor material in the underlying structure and each of the plurality of trenches is juxtaposed with at least one of the ridge channels;
an isolation region in the single shared heterostructure that electrically isolates the planar channel device from the castellated channel device.

5. The circuit of claim 4 , wherein the single shared heterostructure comprises an aluminum gallium nitride (AlGaN) layer overlying a gallium nitride layer (GaN).

6. The circuit of claim 4 , wherein the planar channel device is a d-mode device and the castellated channel device is an e-mode device.

Assignees

• Parke Justin Andrew
• Stewart Eric J
• Howell Robert S
• Henry Howell George
• Nechay Bettina
• Cramer Harlan Carl
• King Matthew Russell
• Gupta Shalini
• Freitag Ronald G
• Renaldo Karen Marie
• Northrop Grumman Systems Corp

Inventors

• Parke Justin Andrew
• Stewart Eric J
• Howell Robert S
• Henry Howell George
• Nechay Bettina
• Cramer Harlan Carl
• King Matthew Russell
• Gupta Shalini
• Freitag Ronald G
• Renaldo Karen Marie

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H01L27/0883 Primary

  Electricity · mapped topic

• H01L21/3081

  Electricity · mapped topic

• H01L29/7786

  Electricity · mapped topic