Semiconductor packages with embedded bridge interconnects

Patent metadata

Field	Value
Publication number	US-10468352-B2
Application number	US-201415503658-A
Country	US
Kind code	B2
Filing date	Sep 19, 2014
Priority date	Sep 19, 2014
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a build-up material;
a bridge interconnect embedded in the build-up material, the bridge interconnect having a first side with a plurality of conductive pads disposed on a first side of the semiconductor package, and a second side opposite the first side, wherein the semiconductor package has an opposing second side, wherein the conductive pads have a first face and a second face opposite the first face, wherein the second face contacts a body of the bridge interconnect;
a via extending through a portion of the build-up material, the via having a first end coupled with a contact disposed on the first side of the semiconductor package, wherein the contact has a first face and an opposing second face wherein the first face of the contact is disposed approximately in a same plane with respective first faces of the conductive pads, wherein the contact is formed from a material that is different from a material of the conductive pads; and
a sacrificial core disposed between the semiconductor package and another semiconductor package to be coupled with the semiconductor package, wherein the other semiconductor package is to form a mirror image of the semiconductor package across the sacrificial core.

2. The semiconductor package of claim 1 , further comprising:
solder resist disposed on the second side of the semiconductor package.

3. The semiconductor package of claim 1 , wherein the second side is a first layer interconnect side and the first side of the semiconductor package is a second layer interconnect side.

4. The semiconductor package of claim 3 , further comprising:
solder resist disposed on the second layer interconnect side.

5. The semiconductor package of claim 1 , wherein the contact and the conductive pads disposed on the first side of the semiconductor package are positioned for coupling with one or more dies.

6. The semiconductor package of claim 1 , wherein the contact comprises nickel.

7. The semiconductor package of claim 1 , wherein the conductive pads are coated in nickel.

8. The semiconductor package of claim 1 , further comprising:
a solder bump disposed on each of the conductive pads.

9. The semiconductor package of claim 1 , wherein the build-up material is an organic build-up material.

10. The semiconductor package of claim 9 , wherein the bridge interconnect is a silicon bridge.

11. The semiconductor package of claim 1 , wherein the conductive pads are free from electrical contact with any vias in the build-up material.

12. The semiconductor package of claim 1 , wherein at least a portion of the first side of the semiconductor package has a profile complementary to a profile of a surface of the sacrificial core.

13. An integrated circuit assembly, comprising:
a die;
a semiconductor package, comprising:
a bridge interconnect embedded in a build-up material, the bridge interconnect having a first side with a plurality of conductive pads disposed on a first side of the semiconductor package, and a second side opposite the first side, wherein the semiconductor package has an opposing second side, wherein the conductive pads have a first face and a second face opposite the first face, wherein the second face contacts a body of the bridge interconnect; and
a via that extends through a portion of the build-up material, the via having a first end coupled with a contact disposed on the first side of the semiconductor package, wherein the contact has a first face and an opposing second face; and

an interposer,
wherein the first face of the contact is disposed approximately in a same plane with respective first faces of the conductive pads, and the die is electrically coupled to the bridge interconnect at the plurality of conductive pads, and wherein the second side of the semiconductor package is a layer interconnect side, and wherein the interposer is electrically coupled to the semiconductor package at the layer interconnect side.

14. The integrated circuit assembly of claim 13 , wherein the plurality of conductive pads are free from being spaced apart by a solder resist material.

15. A method for manufacturing a semiconductor package, comprising:
providing a build-up material on a surface of a sacrificial core;
forming a cavity in the build-up material down to the surface of the sacrificial core;
disposing a bridge interconnect in the cavity, the bridge interconnect having a first side with a plurality of conductive pads and a second side opposite the first side, such that the first side of the bridge interconnect is closer to the surface than the second side of the bridge interconnect is to the surface;
providing additional build-up material to embed the bridge interconnect; and
forming a via in the build-up material, wherein the via extends through a portion of the build-up material, has a first end that is narrower than a second end of the via, and the first end is closer to the surface than the second end is to the surface.

16. The method of claim 15 , further comprising:
removing the sacrificial core to expose the bridge interconnect.

17. The method of claim 15 , wherein the surface is a first surface and the sacrificial core has a second surface opposite the first surface, and wherein the method further comprises:
providing a second build-up material on the second surface of the sacrificial core;
forming a second cavity in the second build-up material down to the second surface of the sacrificial core;
disposing a second bridge interconnect in the second cavity, the second bridge interconnect having a first side with a plurality of conductive pads and a second side opposite the first side, such that the first side of the second bridge interconnect is closer to the second surface than the second side of the second bridge interconnect is to the second surface;
providing additional second build-up material to embed the second bridge interconnect; and
forming a second via in the second build-up material, wherein the second via extends through a portion of the second build-up material, has a first end that is narrower than a second end of the second via, and the first end is closer to the second surface than the second end is to the second surface.

18. A method of manufacturing an integrated circuit assembly, comprising:
embedding a bridge interconnect in a build-up material of a semiconductor package, the bridge interconnect having a first side with a plurality of conductive pads and a second side opposite the first side, wherein the conductive pads have a first face and a second face opposite the first face, wherein embedding includes disposing the plurality of conductive pads on a first side of the semiconductor package such that the second face contacts a body of the bridge interconnect; and
extending a via through a portion of the build-up material, including forming a contact on the first side of the semiconductor package, wherein the contact has a first face and an opposing second face, wherein disposing includes disposing the first face of the contact to be approximately in a same plane with respective first faces of the conductive pads; and coupling the via with the contact;
attaching a vacuum jig to the semiconductor package to hold the first side of the semiconductor package flat; and
attaching a die to the first side of the semiconductor package.

19. The method of claim 18 , wherein the vacuum jig comprises a first vacuum jig component and attaching the vacuum jig to the semiconductor package comprises attaching the

Assignees

• Lee Kyu Oh
• Intel Corp

Inventors

• Lee Kyu-Oh

Classifications

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/07232

  Compression bonding, e.g. thermocompression bonding · CPC title