Methods of forming perpendicular magnetic tunnel junction memory cells having vertical channels

Patent metadata

Field	Value
Publication number	US-10468293-B2
Application number	US-201715857387-A
Country	US
Kind code	B2
Filing date	Dec 28, 2017
Priority date	Dec 28, 2017
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A method of forming a transistor, according to one embodiment, includes: forming an doped material, depositing an oxide layer on the doped material, depositing a conducting layer on the oxide layer, patterning the conducting layer to form at least two word lines, depositing a nitride layer above the at least two word lines, defining at least two hole regions, at each of the defined hole regions, etching down to the doped material through each of the respective word lines, thereby creating at least two holes, depositing a gate dielectric layer on the nitride layer and in the at least two holes, depositing a protective layer on the gate dielectric layer, etching in each of the at least two holes down to the doped material, and removing a remainder of the protective layer.

First claim

What is claimed is:

1. A method of forming a transistor, comprising:
forming a doped material;
depositing an oxide layer on the doped material;
depositing a conducting layer on the oxide layer;
patterning the conducting layer to form at least two word lines;
depositing a nitride layer above the at least two word lines;
defining at least two hole regions;
at each of the defined hole regions, etching down to the doped material through each of the respective word lines, thereby creating at least two holes;
depositing a gate dielectric layer on the nitride layer and in the at least two holes;
depositing a protective layer on the gate dielectric layer;
etching in each of the at least two holes down to the doped material; and
removing a remainder of the protective layer.

2. The method as recited in claim 1 , wherein the doped material is an n+ doped material.

3. The method as recited in claim 2 , wherein the n+ doped material is formed in an active region between a pair of shallow trench isolation (STI) regions.

4. The method as recited in claim 1 , wherein the conducting layer includes a poly-gate material.

5. The method as recited in claim 1 , comprising:
inducing epitaxial silicon structure growth in the at least two holes extending vertically from the doped material;
depositing a second oxide layer on the exposed portions of the epitaxial silicon structures and the gate dielectric layer; and
exposing the planarized nitride layer by performing a chemical-mechanical planarization process.

6. The method as recited in claim 1 , wherein the epitaxial silicon growth is induced using nitrogen sidewall passivation.

7. The method as recited in claim 1 , wherein the epitaxial silicon structures grow past the gate dielectric layer.

8. The method as recited in claim 1 , comprising:
depositing nano-crystalline silicon material on the gate dielectric layer and in the at least two holes;
defining a narrow hole region at each of the at least two hole regions;
at each of the defined narrow hole regions, etching through the nano-crystalline silicon material down to the doped material, wherein a width of each of the narrow hole regions is narrower than a width of a respective one of the at least two hole regions;
filling each of the narrow hole regions with a second oxide material; and
exposing the planarized nitride layer by performing a chemical-mechanical planarization process.

9. The method as recited in claim 8 , wherein the nano-crystalline silicon is deposited at a low temperature.

10. The method as recited in claim 1 , comprising:
depositing nano-crystalline silicon material on the gate dielectric layer and in the at least two holes;
exposing the planarized nitride layer by performing a chemical-mechanical planarization process; and
laser annealing the nano-crystalline silicon material.

11. A method of forming a transistor, comprising:
forming a doped material;
depositing an oxide layer on the doped material;
depositing a conducting layer on the oxide layer;
patterning the conducting layer to form at least two word lines;
depositing a stress inducing nitride layer on the at least two word lines and on the oxide layer;
depositing a nitride layer on the stress inducing nitride layer;
defining at least two hole regions;
at each of the defined hole regions, etching down to the doped material through each of the respective word lines, thereby creating at least two holes;
depositing a gate dielectric layer on the nitride layer and in the at least two holes;
depositing a protective layer on the gate dielectric layer;
etching in each of the at least two holes down to the doped material;
selectively removing a remainder of the protective layer;
depositing an amorphous silicon material on the gate dielectric layer and in the at least two holes;
annealing the amorphous silicon material;
recrystallizing the annealed amorphous silicon material; and
exposing the planarized nitride layer by performing a chemical-mechanical planarization process.

12. The method as recited in claim 11 , wherein the conducting layer includes a poly-gate material.

13. The method as recited in claim 11 , wherein the recrystallization is performed using a laser.

14. The method as recited in claim 11 , wherein the recrystallization is thermally induced.

15. The method as recited in claim 11 , wherein depositing the amorphous silicon material is performed using a tensile stress of the stress inducing nitride layer.

16. A method of forming a transistor, comprising:
depositing a doped silicon material on a substrate;
depositing an un-doped silicon layer;
depositing a second doped silicon layer;
depositing an inter layer dielectric layer;
defining an active region between a pair of shallow trench isolation (STI) regions;
depositing a poly-silicon material in the active region;
patterning the poly-silicon material to form at least two word lines;
depositing an oxide layer on the at least two word lines and on the inter layer dielectric layer;
depositing a nitride layer on the oxide layer;
defining at least two hole regions;
at each of the defined hole regions, etching down to the second doped silicon layer through each of the respective word lines, thereby creating at least two holes;
depositing a gate dielectric layer on the nitride layer and in the at least two holes;
depositing a protective layer on the gate dielectric layer;
etching in each of the at least two holes down to the second doped silicon layer;
selectively removing a remainder of the protective layer;
inducing epitaxial silicon structure growth in the at least two holes extending vertically from the second doped silicon layer; and
exposing the planarized nitride layer by performing a chemical-mechanical planarization process.

17. The method as recited in claim 16 , comprising:
forming a perpendicular magnetic tunnel junction (p-MTJ) sensor structure on each of the epitaxial silicon structures;
forming an extension region on each of the p-MTJ sensor structures; and
forming a common bit line which is electrically coupled to each of the extension regions.

18. The method as recited in claim 16 , wherein defining the active region includes:
applying a mask which defines at least two shallow trench isolation (STI) regions;
etching down to the silicon substrate at each of the defined STI regions;
deposit a oxide layer in the recesses formed by the etching;
depositing a nitride layer on the oxide layer;
depositing a second oxide layer on the nitride layer; and
performing a chemical-mechanical planarization process to define an upper surface of the second oxide layer.

19. The method as recited in claim 16 , wherein the substrate includes silicon.

20. The method as recited in claim 16 , comprising:
etching through the common bit line down into the un-doped silicon layer;
removing the un-doped silicon layer; and
depositing an electrically conductive and non-magnetic material in the etched hole and empty region between the first and second doped silicon layers.

Assignees

• Spin Memory Inc

Inventors

• Kim Kuk-Hwan
• Beery Dafna
• Levi Amitay
• Walker Andrew J

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10 Primary

  Isolation regions comprising dielectric materials · CPC title

• H01L29/7827

  Electricity · mapped topic