Display driving device

Patent metadata

Field	Value
Publication number	US-10467948-B2
Application number	US-201715792946-A
Country	US
Kind code	B2
Filing date	Oct 25, 2017
Priority date	Oct 27, 2016
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

Disclosed is a display driving device capable of reducing an output response delay of an output buffer. The display driving device may include: a first DAC configured to load a first grayscale voltage corresponding to first digital data as a first DAC signal; a second DAC configured to load a second grayscale voltage corresponding to second digital data as a second DAC signal; and an output buffer configured to alternately select the first DAC signal loaded to a first input terminal and the second DAC signal loaded to a second input terminal.

First claim

What is claimed is:

1. A display driving device comprising:
a first digital-to-analog converter (DAC) configured to output a first grayscale voltage corresponding to first digital data as a first DAC signal in an even cycle;
a second DAC configured to output a second grayscale voltage corresponding to second digital data as a second DAC signal in an odd cycle; and
an output buffer comprising a first input terminal to which the first DAC signal is inputted and a second input terminal to which the second DAC signal is inputted, and configured to output a source driving signal by selecting a DAC signal loaded in a previous cycle of a current cycle between the first DAC signal loaded in the even cycle and the second DAC signal loaded in the odd cycle.

2. The display driving device of claim 1 , wherein the output buffer receives a first select signal enabled in the odd cycle and a second select signal enabled in the even cycle, outputs the source driving signal by selecting the first DAC signal loaded to the first input terminal in the odd cycle before the current cycle in response to an enablement of the first select signal, and outputs the source driving signal by selecting the second DAC signal loaded to the second input terminal in the even cycle before the current cycle in response to an enablement of the second select signal.

3. The display driving device of claim 2 , wherein the first select signal and the second select signal are synchronized with an enable timing of an output enable signal for controlling an output of the source driving signal.

4. The display driving device of claim 1 , wherein the output buffer comprises:
an input stage comprising the first input terminal, the second input terminal, a third input terminal for receiving, as a first feedback voltage, a feedback signal of the source driving signal corresponding to the first DAC signal, and a fourth input terminal for receiving, as a second feedback voltage, a feedback signal of the source driving signal corresponding to the second DAC signal, and configured to receive the first select signal and the second select signal which have a periodically and alternately changing enable state, and generate a comparison signal corresponding to the first DAC signal loaded in the even cycle before the current cycle and the first feedback voltage in response to an enablement of the first select signal or generate the comparison signal corresponding to the second DAC signal loaded in the odd cycle before the current cycle and the second feedback voltage in response to an enablement of the second select signal;
a load and bias stage configured to generate a pull-up driving signal and a pull-down driving signal in response to the comparison signal; and
an output stage configured to output the source driving signal using the pull-up driving signal and the pull-down driving signal.

5. The display driving device of claim 4 , wherein the input stage comprises:
first to fourth transistors having the first to fourth input terminals formed at the respective gates thereof;
first to fourth switches connected to the first to fourth transistors, respectively; and
a bias switch connected to the first to fourth transistors in common, and enabled by a bias voltage,
wherein the first and third switches connected to the first and third transistors are controlled by the first select signal, and the second and fourth switches connected to the second and fourth transistors are controlled by the second select signal.

6. The device of claim 4 , wherein the first and second select signals are synchronized with an enable timing of an output enable signal for controlling an output of the source driving signal, the first select signal is enabled in the odd cycle, and the second select signal is enabled in the even cycle.

7. The display driving device of claim 1 , wherein the first DAC and the second DAC share one gamma voltage provider in order to receive the first grayscale voltage and the second grayscale voltage.

8. A display driving device comprising:
a first output unit configured to output a first source driving signal in a negative range of a first supply voltage to a second supply voltage;
a second output unit configured to output a second source driving signal in a positive range of the second supply voltage to a third supply voltage; and
a multiplexer configured to control paths through which the first source driving signal and the second source driving signal are outputted to a display panel,
wherein the first output unit comprises:
a first DAC configured to output a first grayscale voltage of the negative range in response to first digital data as a first DAC signal in an even cycle;
a second DAC configured to output a second grayscale voltage of the negative range response to second digital data as a second DAC signal in an odd cycle; and
a first output buffer comprising a first input terminal to which the first DAC signal is inputted and a second input terminal to which the second DAC signal is inputted, and configured to output the first source driving signal by selecting a DAC signal loaded in a previous cycle of a current cycle between the first DAC signal loaded in the even cycle and the second DAC signal loaded in the odd cycle
wherein the second output unit comprises:
a third DAC configured to output a third grayscale voltage of the positive range in response to third digital data as a third DAC signal in the even cycle;
a fourth DAC configured to output a fourth grayscale voltage of the positive range in response to fourth digital data as a fourth DAC signal in the odd cycle; and
a second output buffer comprising a third input terminal to which the third DAC signal is inputted and a fourth input terminal to which the fourth DAC signal is inputted, and configured to output the second source driving signal by selecting a DAC signal loaded in a previous cycle of a current cycle between the third DAC signal loaded in the even cycle and the fourth DAC signal loaded in the odd cycle.

9. The display driving device of claim 8 , wherein the first output buffer comprises the first input terminal, the second input terminal, a fifth input terminal for receiving, as a first feedback voltage, a feedback signal of the first source driving signal corresponding to the first DAC signal, and a sixth input terminal for receiving, as a second feedback voltage, a feedback signal of the first source driving signal corresponding to the second DAC signal, receives a first select signal and a second select signal which have a periodically and alternately changing enable state, generates a first comparison signal corresponding to the first DAC signal loaded in the even cycle before the current cycle and the first feedback voltage in response to an enablement of the first select signal or generates the first comparison signal corresponding to the second DAC signal loaded in the odd cycle before the current cycle and the second feedback voltage in response to an enablement of the second select signal, and outputs the first source driving signal corresponding to the first comparison signal, and
the second output buffer comprises the third input terminal, the fourth input terminal, a seventh input terminal for receiving, as a third feedback voltage, a feedback signal of the second source driving signal corresponding to the third DAC signal, and an eighth input terminal for receiving, as a fourth feedback voltage, a feedback signal of the second source driving signal corresponding to the fourth DAC signal, receives the first select signal and the second select signal, generates a second comparison signal corresponding to the third DAC signal loaded in the even cycle before the current cycle and the third fee

Assignees

• Silicon Works Co Ltd

Inventors

• Kim Young Bok
• Piao Taiming
• Jeon Hyun Kyu
• Na Joon Ho

Classifications

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/3696

  Generation of voltages supplied to electrode drivers · CPC title

• G09G3/3258

  with pixel circuitry controlling the voltage across the light-emitting element · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title