Source driver, display device with the same and driving method thereof

Patent metadata

Field	Value
Publication number	US-2016180764-A1
Application number	US-201514967785-A
Country	US
Kind code	A1
Filing date	Dec 14, 2015
Priority date	Dec 22, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

A display device includes: a display panel including pixels arranged in a matrix shape; and a source driver to apply data voltages to the pixels. The source driver includes: a shift controller to shift a sampling control signal; a latch array to sample digital video data in response to the sampling control signal shifted by the shift controller; a digital-to-analog converter array to convert the digital video data from the latch array into data voltages by decoding the digital video data and combination-outputting gamma compensation voltages on the basis of a gray value of the decoded data; an output buffer array to output the data voltages from the digital-to-analog converter array; and a bias controller to adjust a bias current, which is applied to the output buffer array, according to delay and stable intervals of the data voltage.

First claim

What is claimed is:

1 . A source driver, comprising:
a shift controller configured to shift a sampling control signal; a latch array configured to sample digital video data in response to the sampling control signal shifted by the shift controller; a digital-to-analog converter array configured to convert the digital video data from the latch array into data voltages by decoding the digital video data and combination-outputting gamma compensation voltages on the basis of a gray value of the decoded data; an output buffer array configured to output the data voltages from the digital-to-analog converter array; and a bias controller configured to adjust a bias current, which is applied to the output buffer array, according to delay and stable intervals of the data voltage.

2 . The source driver of claim 1 , wherein the output buffer array includes a plurality of output buffers which each includes:
an operational amplifier configured to buffer the data voltage from the digital-to-analog converter array; and a bias supplier configured to adjust the bias current in response to a switching control signal from the bias controller and output the adjusted bias current to the operational amplifier.

3 . The source driver of claim 1 , wherein the bias supplier includes:
a current mirror configured to supply the bias voltage to the operational amplifier; a resistor array connected to the current mirror; and at least two switching elements connected to the resistor array and configured to adjust a resistance of the resistor array.

4 . The source driver of claim 2 , wherein the bias supplier includes:
a first constant current source connected to the operational amplifier; a second constant current source connected parallel to the first constant current source; and a switching element used to selectively intercept an output current of the second constant current source in response to the switching control signal from the bias controller.

5 . The source driver of claim 4 , wherein the bias controller includes:
a counter configured to count a number of clocks; a memory configured to store information for a delay interval and a stable interval which are included in an output period of the data voltage; an interval detector configured to detect the delay interval and the stable interval on the basis of a count value from the counter using the information stored the memory; a signal generator configured to derive the switching control signal from the detection resultant of the interval detector.

6 . The source driver of claim 5 , wherein the switching element responsive to the switching control signal intercepts the output current of the second constant current source in the stable interval.

7 . A display device, comprising:
a display panel configured to include a plurality of pixels arranged in a matrix shape; and a source driver which applies data voltages to the pixels and includes:
a shift controller configured to shift a sampling control signal;
a latch array configured to sample digital video data in response to the sampling control signal shifted by the shift controller;
a digital-to-analog converter array configured to convert the digital video data from the latch array into data voltages by decoding the digital video data and combination-outputting gamma compensation voltages on the basis of a gray value of the decoded data;
an output buffer array configured to output the data voltages from the digital-to-analog converter array; and
a bias controller configured to adjust a bias current, which is applied to the output buffer array, according to delay and stable intervals of the data voltage.

8 . The display device of claim 7 , wherein the output buffer array includes a plurality of output buffers which each includes:
an operational amplifier configured to buffer the data voltage from the digital-to-analog converter array; and a bias supplier configured to adjust the bias current in response to a switching control signal from the bias controller and output the adjusted bias current to the operational amplifier.

9 . The display device of claim 8 , wherein the bias supplier includes:
a current mirror configured to supply the bias voltage to the operational amplifier; a resistor array connected to the current mirror; and at least two switching elements connected to the resistor array and configured to adjust a resistance of the resistor array.

10 . The display device of claim 8 , wherein the bias supplier includes:
a first constant current source connected to the operational amplifier; a second constant current source connected parallel to the first constant current source; and a switching element used to selectively intercept an output current of the second constant current source in response to the switching control signal from the bias controller.

11 . The display device of claim 10 , wherein the bias controller includes:
a counter configured to count a number of clocks; a memory configured to store information for a delay interval and a stable interval which are included in an output period of the data voltage; an interval detector configured to detect the delay interval and the stable interval on the basis of a count value from the counter using the information stored the memory; a signal generator configured to derive the switching control signal from the detection resultant of the interval detector.

12 . The display device of claim 11 , wherein the switching element responsive to the switching control signal intercepts the output current of the second constant current source in the stable interval.

13 . A method of driving a display device with a display panel in which a plurality of pixels is arranged in a matrix shape, the method comprising:
defining an output period of a data voltage, which is applied from an output buffer of a source driver to the display panel, into a delay interval and a stable interval; applying a first bias current to an output buffer in the delay interval; and applying a second bias current to the output buffer in the stable interval.

14 . The method of claim 13 , further comprises generating a control signal, which is used to switch the first and second bias currents, using a horizontal synchronous signal and a clock signal.

15 . The method of claim 13 , further comprises generating a control signal, which is used to switch the first and second bias currents, using an input signal of the output buffer and the data voltage.

16 . The method of claim 13 , wherein the first bias current is larger than the second bias current.

Assignees

• Lg Display Co Ltd

Inventors

• Noh Ju Young
• Yang Jun Hyeok
• Woo Kyoung Don

Classifications

• G09G3/3688 Primary

  suitable for active matrices only · CPC title

• H03M1/74

  Simultaneous conversion · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title