Method for processing silicon substrate and method for manufacturing liquid ejection head

US10464325B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10464325-B2
Application numberUS-201715464903-A
CountryUS
Kind codeB2
Filing dateMar 21, 2017
Priority dateMar 24, 2016
Publication dateNov 5, 2019
Grant dateNov 5, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for processing a silicon substrate includes forming a structure having a bottom surface and a depth of 200 μm or more or 300 μm or more from a first surface of a silicon substrate, forming a protective film on an inner wall of the structure, and performing plasma etching so as to selectively remove the protective film disposed on the bottom surface of the structure with respect to the protective film disposed on the substantially perpendicular side wall of the structure, wherein the plasma etching is performed under the condition in which plasma with a sheath length at least 10 times the depth when the depth is 200 μm or more, or at least 5 time the depth when the depth is 300 μm or more, is generated and a mean free path of ions generated in the plasma is longer than the sheath length.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for processing a silicon substrate comprising: forming a structure having a depth of 200 μm or more from a first surface of a silicon substrate, a side wall, and a bottom surface, at least a part of the side wall being substantially perpendicular to the first surface; forming a protective film on an inner wall of the structure, the inner wall comprising the side wall and the bottom surface; and performing plasma etching so as to selectively remove the protective film disposed on the bottom surface of the structure with respect to the protective film disposed on the substantially perpendicular side wall of the structure, wherein the plasma etching is performed under the condition in which plasma with a sheath length at least 10 times the depth of the structure is generated and a mean free path of ions generated in the plasma is equal to or longer than the sheath length. 2. The method for processing a silicon substrate according to claim 1 , wherein the silicon substrate has a surface that is a (100) plane, and at least a part of the side wall, from the bottom surface in the depth direction, of the structure is substantially perpendicular to the first surface. 3. The method for processing a silicon substrate according to claim 1 , wherein the aspect ratio of the structure is 4 or more. 4. The method for processing a silicon substrate according to claim 1 , wherein the depth of the structure is 500 μm or more. 5. The method for processing a silicon substrate according to claim 4 , wherein the structure penetrates the silicon substrate from the first surface to a second surface opposite to the first surface and the bottom surface of the structure is an etching stop layer disposed on the second surface of the silicon substrate. 6. The method for processing a silicon substrate according to claim 1 , wherein an inductively coupled plasma (ICP) etching system is used in the plasma etching. 7. The method for processing a silicon substrate according to claim 1 , wherein the plasma etching is performed by rare gas ion bombardment. 8. The method for processing a silicon substrate according to claim 1 , wherein the protective film is formed by an atomic layer deposition (ALD) method. 9. The method for processing a silicon substrate according to claim 1 , wherein the protective film is composed of any one of SiO 2 , Al 2 O 3 , Ta 2 O 5 , ZrO, TiO 2 , and HfO 2 . 10. A method for processing a silicon substrate comprising: forming a structure having a depth of 300 μm or more from a first surface of a silicon substrate, a side wall, and a bottom surface, at least a part of the side wall being substantially perpendicular to the first surface; forming a protective film on an inner wall of the structure, the inner wall comprising the side wall and the bottom surface; and performing plasma etching so as to selectively remove the protective film disposed on the bottom surface of the structure with respect to the protective film disposed on the substantially perpendicular side wall of the structure, wherein the plasma etching is performed under the condition in which plasma with a sheath length at least 5 times the depth of the structure is generated and a mean free path of ions generated in the plasma is equal to or longer than the sheath length. 11. The method for processing a silicon substrate according to claim 10 , wherein the silicon substrate has a surface that is a (100) plane, and at least a part of the side wall, from the bottom surface in the depth direction, of the structure is substantially perpendicular to the first surface. 12. The method for processing a silicon substrate according to claim 10 , wherein the aspect ratio of the structure is 4 or more. 13. The method for processing a silicon substrate according to claim 10 , wherein the depth of the structure is 500 μm or more. 14. The method for processing a silicon substrate according to claim 13 , wherein the structure penetrates the silicon substrate from the first surface to a second surface opposite to the first surface and the bottom surface of the structure is an etching stop layer disposed on the second surface of the silicon substrate. 15. The method for processing a silicon substrate according to claim 10 , wherein an inductively coupled plasma (ICP) etching system is used in the plasma etching. 16. The method for processing a silicon substrate according to claim 10 , wherein the plasma etching is performed by rare gas ion bombardment. 17. The method for processing a silicon substrate according to claim 10 , wherein the protective film is formed by an atomic layer deposition (ALD) method. 18. The method for processing a silicon substrate according to claim 10 , wherein the protective film is composed of a material selected from the group consisting of SiO 2 , Al 2 O 3 , Ta 2 O 5 , ZrO, TiO 2 , and HfO 2 . 19. A method for manufacturing a liquid ejection head comprising the method for processing a silicon substrate according to claim 1 , further comprising forming, on a second surface opposite to the first surface of the silicon substrate, a flow passage forming member constituting an ejection port for ejecting a liquid and a liquid flow passage that communicates with the ejection port, wherein the structure includes a common liquid chamber composed of the first surface of the silicon substrate and a supply port that communicates with the common liquid chamber and the liquid flow passage from a bottom section of the common liquid chamber. 20. The method for manufacturing a liquid ejection head according to claim 19 , wherein the silicon substrate has a surface that is a (100) plane, and at least a part of the side wall, from the bottom surface in the depth direction, of the structure is substantially perpendicular to the first surface.

Assignees

Inventors

Classifications

  • Structure of the pressure chamber · CPC title

  • Ink-jet print cartridges · CPC title

  • by depositing an etch stop layer, e.g. silicon nitride, silicon oxide, metal · CPC title

  • wet etching · CPC title

  • Processes for functionalising a surface, e.g. provide the surface with specific mechanical, chemical or biological properties · CPC title

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What does patent US10464325B2 cover?
A method for processing a silicon substrate includes forming a structure having a bottom surface and a depth of 200 μm or more or 300 μm or more from a first surface of a silicon substrate, forming a protective film on an inner wall of the structure, and performing plasma etching so as to selectively remove the protective film disposed on the bottom surface of the structure with respect to the …
Who is the assignee on this patent?
Canon Kk
What technology area does this patent fall under?
Primary CPC classification B41J2/1601. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Nov 05 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).