Multicast copy ring for database direct memory access filtering engine

Patent metadata

Field	Value
Publication number	US-10459859-B2
Application number	US-201615362673-A
Country	US
Kind code	B2
Filing date	Nov 28, 2016
Priority date	Nov 28, 2016
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine. Tabular data is efficiently copied between internal memories of the data movement system via a copy ring that is coupled to the internal memories of the data movement system and/or is coupled to a data movement engine. Also, a data movement engine internally broadcasts data to other data movement engines, which then transfer the data to respective core processors. Partitioning may also be performed by the hardware of the data movement system. Techniques are used to partition data “in flight”. The data movement system also generates a column of row identifiers (RIDs). A row identifier is a number treated as identifying a row or element's position within a column. Row identifiers each identifying a row in column are also generated.

First claim

What is claimed is:

1. A method, comprising:
in response to a particular memory location being pushed into a first register within a first register space that is accessible by a first set of electronic circuits:
said first set of electronic circuits accessing a descriptor stored at the particular memory location, wherein the descriptor indicates:
a width of a column of tabular data, a number of rows of said tabular data;
a source memory address specifying a memory address for said tabular data in a source memory unit of a plurality of memory units;
a destination memory address specifying a relative address within each memory unit of said plurality of memory units;
a write map specifying which of said plurality of memory units to write said tabular data;

the first set of electronic circuits determining, based on the descriptor, control information, said control information including said write map;
the first set of electronic circuits transmitting, using a hardware data channel, the control information to a second set of electronic circuits;
according to the control information, said second set of electronic circuits copying said tabular data from said source memory unit to each memory unit of said plurality of memory units specified by said write map.

2. The method of claim 1 , wherein said tabular data is a bit vector, wherein said second set of electronic circuits:
based on a copy of said bit vector stored in a first memory unit of said plurality of memory units, performing one or more tabular data manipulation operations on first other tabular data; and
based on a copy of said bit vector stored in a second memory unit of said plurality of memory units, performing one or more tabular data manipulation operations on second other tabular data.

3. The method of claim 1 , wherein said tabular data is a RID column, wherein said second set of electronic circuits:
based on a copy of said RID column stored in a first memory unit of said plurality of memory units, performing one or more tabular data manipulation operations on first other tabular data; and
based on a copy of said RID column stored in a second memory unit of said plurality of memory units, performing one or more tabular data manipulation operations on second other tabular data.

4. The method of claim 1 ,
wherein said second set of electronic circuits comprise a plurality of copy ring nodes, each copy ring node of said plurality of copy ring nodes connected by a first bus to a source copy ring node and a second bus to a destination copy ring node;
wherein said plurality of copy ring nodes includes a plurality of copy memory interface nodes, each copy memory interface node being configured to write and read from one or more respective memory units of said plurality of memory units;
wherein the method further includes each copy memory interface node of a set of one or more of said plurality of copy memory interface nodes receiving said control information from the respective source copy node of said each copy memory interface node.

5. The method of claim 4 , wherein said each copy memory interface node of a set of one or more of said plurality of copy memory interface nodes receiving said control information includes a particular copy memory interface node receiving said control information, wherein the method further includes:
in response to said particular copy memory interface node receiving said control information, said particular copy memory interface node detecting that said write map specifies to write said tabular data to the respective one or more memory units of said plurality of memory units; and
in response to said particular copy memory interface node detecting that said write map specifies to write said tabular data to the respective one or more memory units of said plurality of memory units:
writing said tabular data to a respective memory unit of said particular copy memory interface node at said destination memory address, said tabular data being forwarded to said particular copy memory interface node by the respective source copy ring node of said particular copy memory interface node, and
setting said write map to not specify to write said tabular data to the respective memory unit of said particular copy memory interface node.

6. The method of claim 5 , further including:
after setting said write map, said particular copy memory interface node detecting that said write map specifies to write to another memory unit of said plurality of memory units;
in response to detecting that said write map specifies to write to another memory unit of said plurality of memory units, forwarding said tabular data to the respective destination node of said particular copy memory interface node.

7. The method of claim 5 , further including:
after setting said write map, said particular copy memory interface node detecting that said write map does not specify to write to another memory unit of said plurality of memory units;
in response to detecting that said write map does not specify to write to another memory unit of said plurality of memory units, ceasing to forward said tabular data to the respective destination particular copy memory interface node of said particular copy memory interface node.

8. The method of claim 4 , wherein said each copy memory interface node of a set of one or more of said plurality of copy memory interface nodes receiving said control information includes a particular copy memory interface node receiving said control information, wherein the method further includes:
said particular copy memory interface node detecting that said source memory address identifies said tabular data in the respective memory unit of said particular copy memory interface node;
in response detecting that said source memory address identifies said tabular data in the respective memory unit of said particular copy memory interface node, said particular copy memory interface node:
reading said tabular data from the respective memory unit of said particular copy memory interface node; and
transmitting said tabular data to the respective destination copy memory interface node of said particular copy memory interface node.

9. The method of claim 8 ,
detecting that said write map specifies to write said tabular data to the respective memory unit of said particular copy memory interface node; and
in response to said particular copy memory interface node detecting that said write map specifies to write said tabular data to the respective memory unit of said particular copy memory interface node, writing said tabular data to the respective memory unit of said particular copy memory interface node at said destination memory address, said tabular data being forwarded to said particular copy memory interface node by the respective source copy ring node of said particular copy memory interface node.

10. The method of claim 4 , further including:
wherein said plurality of copy ring nodes include one copy engine node;
wherein said copy engine node is connected to a controller;
wherein said copy engine node receives second control information, wherein said second control information specifies:
a width of a column of second tabular data and a number of rows of said second tabular data;
a source memory address specifying a memory address for said second tabular data in a source memory unit of a plurality of memory units.

11. The method of claim 10 , further including
a particular copy memory interface node of said plurality of copy memory interface nodes receiving said control information;
said particular copy memory interface node detecting that said source address identifies an address in the resp

Assignees

• Oracle Int Corp

Inventors

• Jain Rishabh
• Brown David A
• Duller Michael

Classifications

• G06F13/102

  where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title