Semiconductive structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10457549-B2
Application number	US-201715618914-A
Country	US
Kind code	B2
Filing date	Jun 9, 2017
Priority date	Feb 3, 2017
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

A semiconductive structure includes a first substrate comprising an interconnection layer and a first conductor protruding from the interconnection layer, a second substrate comprising a second conductor bonded with the first conductor, a first cavity between and sealed by the first substrate and the second substrate and the first cavity has a first cavity pressure, a second cavity between and sealed by the first substrate and the second substrate and the second cavity has a second cavity pressure, a first surface of the interconnection layer is a sidewall of the first cavity, wherein the first cavity pressure is less than the second cavity pressure.

First claim

What is claimed is:

1. A semiconductive structure, comprising:
a first substrate comprising:
an interconnection layer; and
a first conductor protruding from the interconnection layer;

a second substrate comprising a second conductor bonded to the first conductor;
a first cavity between and sealed by the first substrate and the second substrate, wherein the first cavity has a first cavity pressure; and
a second cavity between and sealed by the first substrate and the second substrate, wherein the second cavity has a second cavity pressure,
wherein the first cavity partially extends through the interconnection layer, and a first surface of the interconnection layer is a sidewall of the first cavity;
the first cavity pressure is less than the second cavity pressure;
a bottommost surface of the second cavity is substantially co-planar with a second surface of the interconnection layer substantially orthogonal to the first surface; and
the second cavity is defined by the second surface of the interconnection layer and a surface of the second substrate, a surface of the first conductor and a surface of the second conductor.

2. The semiconductive structure of claim 1 , further comprising an outgassing layer in the second cavity, wherein the outgassing layer is on the bottommost surface of the second cavity.

3. The semiconductive structure of claim 2 , wherein the outgassing layer comprises an oxide.

4. The semiconductive structure of claim 2 , wherein the outgassing layer comprises argon.

5. The semiconductive structure of claim 1 , wherein the second cavity pressure is about 1 atm.

6. The semiconductive structure of claim 1 , wherein a first device is positioned at the first cavity and a second device is positioned at the second cavity.

7. The semiconductive structure of claim 6 , wherein the first device is a gyroscope and the second device is an accelerometer.

8. A semiconductive structure, comprising:
a first substrate having an interconnection layer and a plurality of first conductors protruding from the interconnection layer;
a second substrate in contact with the first substrate via a portion of the plurality of first conductors;
a plurality of cavities between and sealed by the first substrate and the second substrate;
wherein the plurality of cavities comprises at least two different pressures;
wherein one of the plurality of cavities has a higher pressure with a first bottommost surface substantially co-planar with a surface of the interconnection layer, and another one of the plurality of cavities has a lower pressure with a second bottommost surface substantially lower than the surface of the interconnection layer, the one of the plurality of cavities is defined by the surface of the interconnection layer, a surface of the second substrate and a surface of the plurality of first conductors, and the another one of the plurality of cavities partially extends through the interconnection layer.

9. The semiconductive structure of claim 8 , wherein one of the plurality of the first conductors provides a sidewall for one of the plurality of cavities.

10. The semiconductive structure of claim 8 , wherein the second substrate is eutectically bonded to the first substrate.

11. The semiconductive structure of claim 8 , wherein the second bottommost surface is substantially lower than the first bottommost surface.

12. The semiconductive structure of claim 8 , further comprising an outgassing layer on the surface of the interconnection layer.

13. The semiconductive structure of claim 12 , wherein the outgassing layer protrudes from the surface of the interconnection layer and extends to a first height.

14. The semiconductive structure of claim 8 , wherein one of the plurality of the first conductors is adjacent to the interconnection layer.

15. A semiconductive structure, comprising:
a bulk substrate comprising:
an active device formed in proximity to a surface of the bulk substrate; and
an interconnection layer disposed over the bulk substrate and electrically coupled to the active device;

a bonding substrate, hermetically bonded to the bulk substrate through a plurality of conductors, wherein a first cavity and a second cavity are formed between the bonding substrate and the bulk substrate;
wherein the first cavity is in a vacuum pressure and the second cavity is in a pressure higher than the vacuum pressure; and
wherein a distance from a bottommost surface of the first cavity to the surface of the bulk substrate is less than a distance from a bottommost surface of the second cavity to the surface of the bulk substrate, and the second cavity is defined by a surface of the interconnection layer, a surface of the bonding substrate, and a surface of the plurality of conductors.

16. The semiconductive structure of claim 15 , wherein the first cavity is hermetically isolated from the second cavity.

17. The semiconductive structure of claim 15 , further comprising an outgassing layer disposed in the second cavity on the surface of the interconnection layer.

18. The semiconductive structure of claim 15 , further comprising a device hermetically sealed in the first cavity.

19. The semiconductive structure of claim 15 , wherein a portion of the interconnection layer is recessed from a top surface of the interconnection layer to have a depth in the first cavity.

20. The semiconductive structure of claim 19 , wherein the recessed portion of the interconnection layer forms a sidewall of the first cavity.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Manfacturing Company Ltd

Inventors

• Liu Yen-Cheng
• Hsieh Cheng-Yu
• Tsai Shang-Ying
• Chang Kuei-Sung

Classifications

• B81C2203/037

  Thermal bonding techniques not provided for in B81C2203/035 - B81C2203/036 · CPC title

• B81C2203/036

  Fusion bonding · CPC title

• B81C2203/0118

  Bonding a wafer on the substrate, i.e. where the cap consists of another wafer · CPC title

• B81C2203/0792

  Forming interconnections between the electronic processing unit and the micromechanical structure · CPC title

• B81B2203/0315

  Cavities · CPC title