Threshold adjustment compensation of asymmetrical optical noise

Patent metadata

Field	Value
Publication number	US-10454580-B2
Application number	US-201816154448-A
Country	US
Kind code	B2
Filing date	Oct 8, 2018
Priority date	Feb 10, 2017
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

An optical data circuit includes threshold adjustment circuits to perform threshold adjustment compensation of asymmetrical optical noise. The optical data circuit includes an optical-to-electrical conversion circuit configured to produce first and second differential electrical data signals, at respective first and second electrical nodes, in response to an optical data signal. First and second digital-to-analog converter (DAC) circuits are each respectively coupled to the first and second electrical nodes and configured to respectively generate first and second adjustment signals. The first and second DAC circuits are configured to adjust the first and second differential electrical data signals such that a zero-crossing point of positive data is pulled up in response to the first adjustment signal and a zero-crossing point of negative data is pulled down in response to the second adjustment signal.

First claim

What is claimed is:

1. An optical data circuit comprising:
an optical-to-electrical conversion circuit configured to produce differential electrical data signals, at respective electrical nodes, in response to an optical data signal; and
digital-to-analog converter (DAC) circuitry coupled to the respective electrical nodes and configured to generate at least one adjustment signal to adjust a zero-crossing point of the differential electrical data signals.

2. The circuit of claim 1 , wherein the differential electrical data signals comprise a negative data signal and a positive data signal, and the DAC circuitry is configured to:
pull up a zero-crossing point of the positive data signal and pull down a zero-crossing point of the negative data signal based on the at least one adjustment signal.

3. The circuit of claim 2 , wherein the DAC circuitry includes first and second R-2R DAC circuits, each of the R-2R DAC circuits comprising a plurality of selection circuits to select a respective resistor voltage divider circuit in response to at least one select control word.

4. The circuit of claim 3 , further comprising:
a threshold adjustment control circuit coupled to the DAC circuitry, the threshold adjustment control circuit configured to generate the at least one select control word.

5. The circuit of claim 4 , wherein the threshold adjustment control circuit is configured to generate the at least one select control word based on a hard-wired default code and circuit characteristics of the threshold adjustment control circuit.

6. The circuit of claim 5 , wherein the at least one select control word comprises a first select control word and a second select control word, and the DAC circuitry is configured to:
adjust the zero-crossing point of the positive data signal in response to the first select control word; and
adjust the zero-crossing point of the negative data signal in response to the second select control word.

7. The circuit of claim 1 , further comprising a termination circuit coupled to at least a first electrical node and a second electrical node of the respective electrical nodes.

8. The circuit of claim 7 , further comprising:
a first capacitance coupled between the first electrical node and a first DAC circuit of the DAC circuitry; and
a second capacitance coupled between the second electrical node and a second DAC circuit of the DAC circuitry.

9. The circuit of claim 8 , wherein each of the first and second DAC circuits of the DAC circuitry is respectively coupled to the first and second capacitances through a respective first and second resistance.

10. The circuit of claim 9 , wherein the first and second resistances comprise a resistance value large enough to avoid signal DC wandering of the differential electrical data signals at respective inputs to a linear equalizer circuit.

11. An optical communication system comprising:
an optical-to-electrical conversion circuit configured to produce differential electrical data signals, at respective electrical nodes, in response to an optical data signal;
a termination circuit coupled to the respective electrical nodes;
digital-to-analog converter (DAC) circuitry coupled to the respective electrical nodes, the DAC circuit comprising a plurality of binary inputs and a corresponding voltage output; and
a linear equalizer circuit coupled to the termination circuit and the DAC circuitry, wherein the DAC circuitry is configured to adjust a zero-crossing point of at least one of the differential electrical data signals based on the voltage output.

12. The system of claim 11 , further comprising a clock and data recovery circuit coupled to differential outputs of the linear equalizer circuit, the clock and data recovery circuit configured to re-time the differential electrical data signals.

13. The system of claim 12 , further comprising a driver circuit coupled to the clock and data recovery circuit, the driver circuit configured to transmit the re-timed differential electrical data signals to a host.

14. The system of claim 11 , wherein the termination circuit comprises a first resistance coupled between a first electrical node of the respective electrical nodes and a power supply node, and a second resistance coupled between a second electrical node of the respective electrical nodes and the power supply node.

15. The system of claim 11 , further comprising a threshold adjustment control circuit coupled to the DAC circuitry and configured to generate positive and negative select words at the binary inputs for adjusting the zero-crossing point.

16. A method for threshold adjustment compensation of optical noise when generating electrical data signals from an optical data signal, the method comprising:
converting the optical data signal to differential electrical data signals;
generating a plurality of threshold adjust signals based on a default code and circuit characteristics;
adjusting a zero-crossing point of at least one of the differential electrical data signals based on at least one of the threshold adjust signals such that a zero-crossing point of the differential electrical data signals is adjusted based on data polarity; and
equalizing the differential electrical data signals after the adjusting of the zero-crossing point to generate the electrical data signals.

17. The method of claim 16 , further comprising re-timing the electrical data signals to recover positive and negative data.

18. The method of claim 16 , wherein generating the threshold adjust signals comprises:
receiving a value representative of common circuit deviation characteristics;
receiving a value of a desired voltage difference;
adding the value representative of the common circuit deviation characteristics to a stored common circuit characteristics code and the value of the desired voltage difference to generate a positive select control word; and
subtracting the value of the desired voltage difference from a sum of the value representative of the common circuit deviation characteristics and the stored common circuit characteristics code to generate a negative select control word.

19. The method of claim 18 , further comprising:
generating a first threshold adjust signal of the plurality of threshold adjust signals by a first digital-to-analog converter (DAC) circuit with the positive select control word; and
generating a second threshold adjust signal of the plurality of threshold adjust signals by a second DAC circuit with the negative select control word.

20. The method of claim 19 , wherein the positive select control word and the negative select control word selects one or more of a plurality of voltage divider circuits in the first or second DAC circuits to generate the first or second threshold adjust signals.

Assignees

• Futurewei Technologies Inc

Inventors

• Gu Liang
• Lee Hung-Yi
• Cao Yuming
• Liu Miao

Classifications

• H04B3/04

  Control of transmission; Equalising · CPC title

• H04B10/695 Primary

  Arrangements for optimizing the decision element in the receiver, e.g. by using automatic threshold control · CPC title

• H04B10/2507 Primary

  for the reduction or elimination of distortion or dispersion · CPC title

• H03L7/0807

  concerning mainly a recovery circuit for the reference signal · CPC title

• H04B10/697

  Arrangements for reducing noise and distortion · CPC title