Threshold adjustment compensation of asymmetrical optical noise

Patent metadata

Field	Value
Publication number	US-10097266-B2
Application number	US-201715429492-A
Country	US
Kind code	B2
Filing date	Feb 10, 2017
Priority date	Feb 10, 2017
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

An optical data circuit includes threshold adjustment circuits to perform threshold adjustment compensation of asymmetrical optical noise. The optical data circuit includes an optical-to-electrical conversion circuit configured to produce first and second differential electrical data signals, at respective first and second electrical nodes, in response to an optical data signal. First and second digital-to-analog converter (DAC) circuits are each respectively coupled to the first and second electrical nodes and configured to respectively generate first and second adjustment signals. The first and second DAC circuits are configured to adjust the first and second differential electrical data signals such that a zero-crossing point of positive data is pulled up in response to the first adjustment signal and a zero-crossing point of negative data is pulled down in response to the second adjustment signal.

First claim

What is claimed is:

1. An optical data circuit comprising:
an optical-to-electrical conversion circuit configured to produce first and second differential electrical data signals, at respective first and second electrical nodes, in response to an optical data signal;
a first digital-to-analog converter (DAC) circuit coupled to the first electrical node and configured to generate a first adjustment signal; and
a second DAC circuit coupled to the second electrical node and configured to generate a second adjustment signal;
wherein the first and second DAC circuits are configured to adjust the first and second differential electrical data signals such that a zero-crossing point of a positive data signal is pulled up in response to the first adjustment signal and a zero-crossing point of a negative data signal is pulled down in response to the second adjustment signal.

2. The circuit of claim 1 , wherein the first and second DAC circuits include first and second R-2R DAC circuits comprising a plurality of selection circuits to select a respective resistor voltage divider circuit in response to a respective first or second select control word.

3. The circuit of claim 2 , further comprising a threshold adjustment control circuit coupled to the first and second DAC circuits, the threshold adjustment control circuit configured to generate first and second select control words.

4. The circuit of claim 3 , wherein the threshold adjustment control circuit is configured to generate the first and second select control words based on a hard-wired default code and circuit characteristics.

5. The circuit of claim 4 , wherein the first DAC circuit adjusts the zero-crossing point of the positive data in response to the first select control word and the second DAC circuit adjusts the zero-crossing point of the negative data in response to the second select control word.

6. The circuit of claim 1 , further comprising a termination circuit coupled to the first and second electrical nodes.

7. The circuit of claim 6 , further comprising:
a first capacitance coupled between the first electrical node and the first DAC circuit; and
a second capacitance coupled between the second electrical node and the second DAC circuit.

8. The circuit of claim 7 , wherein each of the first and second DAC circuits is respectively coupled to the first and second capacitances through a respective first and second resistance.

9. The circuit of claim 8 , wherein the first and second resistances comprise a resistance value large enough to avoid signal DC wandering of the positive and negative data at respective inputs to a linear equalizer circuit.

10. An optical communication system comprising:
an optical-to-electrical conversion circuit configured to produce first and second differential electrical data signals, at respective first and second electrical nodes, in response to a single-ended optical data signal;
a termination circuit coupled to the first and second electrical nodes;
a first digital-to-analog converter (DAC) circuit coupled to the first electrical node, the first DAC circuit comprising a first binary input and a first voltage output;
a second DAC circuit coupled to the second electrical node, the second DAC circuit comprising a second binary input and a second voltage output; and
a linear equalizer circuit coupled to the termination circuit and the first and second DAC circuits; and
wherein the first and second DAC circuits are configured to adjust the first and second differential electrical data signals based on the respective first and second voltage outputs such that a zero-crossing point of a positive data signal is pulled up and a zero-crossing point of a negative data signal is pulled down.

11. The system of claim 10 , further comprising a clock and data recovery circuit coupled to differential outputs of the linear equalizer circuit, the clock and data recovery circuit configured to re-time the differential electrical data signals.

12. The system of claim 11 , further comprising a driver circuit coupled to the clock and data recovery circuit, the driver circuit configured to transmit the re-timed differential electrical data signals to a host.

13. The system of claim 10 , wherein the termination circuit comprises a first resistance coupled between the first electrical node and a power supply node and a second resistance coupled between the second electrical node and the power supply node.

14. The system of claim 10 , further comprising a threshold adjustment control circuit coupled to the first and second DAC circuits and configured to generate positive and negative select words respectively at the first and second binary inputs.

15. A method for threshold adjustment compensation of optical noise when generating electrical data signals from an optical data signal, the method comprising:
converting the optical data signal to first and second differential electrical data signals;
generating first and second threshold adjust signals based on a default code and circuit characteristics;
adjusting a zero-crossing point of the first and second differential data signals based on the respective first and second threshold adjust signals such that the zero-crossing point of positive data is pulled up and the zero-crossing point of negative data is pulled down; and
equalizing the first and second differential data signals after the zero-crossing points of each signal has been adjusted to generate the electrical data signals.

16. The method of claim 15 , further comprising re-timing the electrical data signals to recover the positive and negative data.

17. The method of claim 15 , wherein generating the first and second threshold adjust signals comprises:
receiving a value representative of common circuit deviation characteristics;
receiving a value of the desired voltage difference;
adding the value representative of the common circuit deviation characteristics to a stored common circuit characteristics code and the value of the desired voltage difference to generate a positive select control word; and
subtracting the value of the desired voltage difference from the sum of the value representative of the common circuit deviation characteristics and the stored common circuit characteristics code to generate a negative select control word.

18. The method of claim 17 , further comprising generating the first threshold adjust signal by a first digital-to-analog converter (DAC) circuit with the positive select control word.

19. The method of claim 18 , further comprising generating the second threshold adjust signal by a second DAC circuit with the negative select control word.

20. The method of claim 19 , wherein the positive select control word and the negative select control word selects one or more of a plurality of voltage divider circuits in the first or second DAC circuits to generate the first or second adjust signals.

Assignees

• Futurewei Technologies Inc

Inventors

• Gu Liang
• Lee Hung-Yi
• Cao Yuming
• Liu Miao

Classifications

• H04B3/04

  Control of transmission; Equalising · CPC title

• H03L7/0807

  concerning mainly a recovery circuit for the reference signal · CPC title

• H04B10/697

  Arrangements for reducing noise and distortion · CPC title

• H04B10/695 Primary

  Arrangements for optimizing the decision element in the receiver, e.g. by using automatic threshold control · CPC title

• H04B10/2507 Primary

  for the reduction or elimination of distortion or dispersion · CPC title