Calibrated biasing of sleep transistor in integrated circuits

Patent metadata

Field	Value
Publication number	US-10454476-B2
Application number	US-201816145598-A
Country	US
Kind code	B2
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

Embodiments include apparatuses, methods, and systems associated with biasing a sleep transistor (also referred to as a power gate transistor) in an integrated circuit. The sleep transistor may be coupled between a load circuit and a power rail, the sleep transistor to be on in an active mode to provide the supply voltage to the load circuit, and to be off in a sleep mode to disconnect the load circuit from the power rail. The bias circuit may be coupled to the gate terminal of the sleep transistor to provide a calibrated gate voltage to the gate terminal during the sleep mode. The calibrated gate voltage may be based on a subthreshold leakage current and a gate-induced drain leakage (GIDL) current of the sleep transistor or a replica sleep transistor designed to replicate the leakage current of the sleep transistor. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. A circuit comprising:
a load circuit;
a power rail to receive a supply voltage;
a sleep transistor coupled between the load circuit and the power rail, the sleep transistor to be on in an active mode to provide the supply voltage to the load circuit, and to be off in a sleep mode to disconnect the load circuit from the power rail; and
a bias circuit coupled to the sleep transistor to provide a calibrated gate voltage to a gate terminal of the sleep transistor during the sleep mode, wherein the bias circuit includes a replica sleep transistor and is to:
measure a total leakage current of the replica sleep transistor at a plurality of voltage levels of a gate voltage provided to the replica sleep transistor, wherein the total leakage current includes a subthreshold leakage current and a gate-induced drain leakage (GIDL) current of the replica sleep transistor; and
set the calibrated gate voltage to a calibrated voltage level that has a lowest measured total leakage current among the plurality of voltage levels, wherein the subthreshold leakage current is approximately equal to the GIDL current plus a junction leakage current of the replica sleep transistor at the calibrated gate voltage.

2. The circuit of claim 1 , wherein a source terminal of the replica sleep transistor is coupled to an internal node of the bias circuit, and wherein the bias circuit further includes:
a capacitor coupled between the internal node and ground;
a controller to charge the internal node to an initial voltage; and
a voltage detector to detect when a voltage at the internal node falls below a threshold voltage;
wherein the bias circuit is to measure the total leakage current of the replica sleep transistor based on a time period that elapses for the voltage at the internal node to fall below the threshold voltage.

3. The circuit of claim 1 , wherein the bias circuit is to adjust a voltage level of the gate voltage by a voltage step for successive measurements until the measured total leakage current for a first iteration is greater than the measured total leakage current for a prior iteration.

4. The circuit of claim 1 , wherein the bias circuit is to set the calibrated voltage level of the calibrated gate voltage to be greater than, equal to, or less than the supply voltage based on the total leakage current.

5. The circuit of claim 1 , wherein the bias circuit is to provide the calibrated gate voltage to a plurality of sleep transistors of the circuit.

6. The circuit of claim 1 , wherein the sleep transistor is a first sleep transistor, and wherein the circuit further comprises a second sleep transistor coupled between the bias circuit and the power rail to power gate circuitry of the bias circuit after the calibrated gate voltage is set.

7. The circuit of claim 1 , wherein the bias circuit is to periodically reset the calibrated voltage level of the calibrated gate voltage during the sleep mode.

8. The circuit of claim 1 , wherein the bias circuit is on a same integrated circuit die as the load circuit and the sleep transistor.

9. A bias circuit to provide a calibrated gate voltage to a sleep transistor during a sleep mode, the bias circuit comprising:
a replica sleep transistor having a source terminal coupled to an internal node of the bias circuit;
a voltage generator to provide a gate voltage to the replica sleep transistor and the sleep transistor; and
a control circuit to, for a plurality of voltage levels of the gate voltage:
charge the internal node to an initial voltage;
determine a time period that elapses for a voltage level at the internal node to fall to a threshold voltage that is less than the initial voltage; and
set the calibrated gate voltage to a calibrated voltage level that is associated with a longest determined time period from among the plurality of voltage levels.

10. The bias circuit of claim 9 , further comprising a capacitor coupled between the internal node and ground.

11. The bias circuit of claim 9 , wherein the control circuit is coupled in a closed loop with the replica sleep transistor and the voltage generator to set the calibrated gate voltage to the calibrated voltage level.

12. The bias circuit of claim 9 , wherein the time period is indicative of a total leakage current of the replica sleep transistor, and wherein the total leakage current includes a subthreshold leakage current, a gate-induced drain leakage (GIDL) current, and a junction leakage current of the replica sleep transistor.

13. The bias circuit of claim 9 , wherein the bias circuit is to adjust a voltage level of the gate voltage by a voltage step for successive determinations of the time period until the determined time period for a first iteration is greater than the determined time period for a prior iteration, and wherein the voltage level associated with the prior iteration is the calibrated voltage level.

14. The bias circuit of claim 9 , wherein the bias circuit is to adjust the calibrated voltage level within a range that includes a first voltage level that is greater than a supply voltage and a second voltage level that is less than the supply voltage.

15. The bias circuit of claim 9 , wherein a subthreshold leakage current of the replica sleep transistor is approximately equal to a GIDL current plus a junction leakage current of the replica sleep transistor at the calibrated gate voltage.

16. The bias circuit of claim 9 , wherein the bias circuit is to provide the calibrated gate voltage to a plurality of sleep transistors of the circuit.

17. A computer system comprising:
a battery;
one or more antennas; and
a processor coupled to the battery and the one or more antennas, the processor including:
a logic circuit;
a sleep transistor coupled between the logic circuit and a power supply rail to switch the logic circuit between an active mode and a sleep mode; and
a bias circuit coupled to a gate terminal of the sleep transistor to calibrate a gate voltage provided to the gate terminal with a closed control loop that adjusts a voltage level of the calibrated gate voltage based on a total leakage current through a replica sleep transistor, wherein the total leakage current includes a subthreshold leakage current a gate-induced drain leakage (GIDL) current, and a junction leakage current of the replica sleep transistor, wherein the subthreshold leakage current is approximately equal to the GIDL current plus the junction leakage current of the replica sleep transistor at the calibrated gate voltage.

18. The computer system of claim 17 , wherein the replica sleep transistor has a source terminal coupled to an internal node of the bias circuit, and wherein the bias circuit further includes:
a voltage generator to provide a gate voltage to the replica sleep transistor and the sleep transistor; and
a control circuit to, for a plurality of voltage levels of the gate voltage:
charge the internal node to an initial voltage;
determine a time period that has elapsed for a voltage level at the internal node to fall to a threshold voltage that is less than the initial voltage; and
set the calibrated gate voltage to a calibrated voltage level that is associated with a longest determined time period from among the plurality of voltage levels.

19. The computer system of claim 17 , wherein the bias circuit is to adjust the calibrated gate voltage within a range that includes a first voltage level that is greater than a supply voltage, of the power supply rail, and a second voltage level that is less than the suppl

Assignees

• Intel Corp

Inventors

• Bang Suyoung
• Khellah Muhammad
• Augustine Charles
• Meinerzhagen Pascal
• Cho Minki

Classifications

• H03K19/0016 Primary

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title

• H03K19/0013

  in field effect transistor circuits · CPC title