Systems and methods for fabrication of superconducting integrated circuits

Patent metadata

Field	Value
Publication number	US-10453894-B2
Application number	US-201815956404-A
Country	US
Kind code	B2
Filing date	Apr 18, 2018
Priority date	Feb 25, 2009
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.

First claim

We claim:

1. A method of fabricating a superconducting integrated circuit, the method comprising:
depositing a dielectric layer to overlie a substrate, the dielectric layer including an exposed upper surface;
etching the exposed upper surface of the dielectric layer to form a trench in the dielectric layer, the etching including performing a photolithographic process;
depositing a metal layer to overlie the dielectric layer, the metal layer comprising a first and a second portion, the first portion of the metal layer deposited on an unetched portion of the exposed upper surface of the dielectric layer and the second portion of the metal layer deposited in the trench; and
planarizing the metal layer to remove at least some of the first portion of the metal layer, wherein depositing a metal layer to overlie the dielectric layer includes depositing a material that superconducts at or below a critical temperature.

2. The method of claim 1 , wherein depositing a dielectric layer to overlie a substrate includes depositing a non-oxide-based dielectric.

3. The method of claim 1 , wherein planarizing the metal layer to remove at least some of the first portion of the metal layer includes planarizing the metal layer to form a metal trace that is embedded in the dielectric layer.

4. The method of claim 1 , wherein planarizing the metal layer to remove at least some of the first portion of the metal layer includes planarizing the metal layer to form a first electrode of a Josephson junction, the method further comprising depositing an electrically insulative layer over at least a portion of the first electrode, and depositing a second electrode of the Josephson junction, wherein depositing a second electrode of the Josephson junction includes depositing a material that superconducts at or below a critical temperature.

5. The method of claim 1 , further comprising:
depositing an additional dielectric layer over at least a portion of the metal layer;
planarizing a surface of the additional dielectric layer;
forming a hole in the additional dielectric layer to expose at least a portion of the metal layer; and
at least partially filing the hole in the additional dielectric layer with a material that superconducts at or below a critical temperature.

6. The method of claim 1 , wherein depositing a dielectric layer to overlie a substrate includes depositing a dielectric layer to overlie a substrate that comprises at least one material selected from the group consisting of: silicon, and sapphire.

7. The method of claim 1 , wherein depositing a dielectric layer to overlie a substrate includes depositing a dielectric layer that includes at least one of silicon dioxide (SiO2), silicon nitride (SiN), hydrogenated amorphous silicon, and an organic polymer dielectric.

8. The method of claim 1 , wherein depositing a dielectric layer to overlie a substrate includes depositing a dielectric layer that includes silicon dioxide.

9. The method of claim 1 , wherein etching a trench into the exposed upper surface of the dielectric layer includes:
depositing a photoresist over at least a portion of the dielectric layer;
masking and developing the photoresist to produce an area of the dielectric layer not covered by the photoresist;
removing the area of the dielectric layer not covered by the photoresist; and
removing the photoresist.

10. The method of claim 9 , wherein removing the area of the dielectric layer not covered by the photoresist includes etching by a dry chemical etching process.

11. The method of claim 9 , wherein removing the photoresist includes etching by a wet chemical etching process.

12. The method of claim 1 , wherein depositing a material that superconducts at or below a critical temperature includes depositing a material that is comprised of at least one material selected from the group consisting of: niobium, aluminum, zinc, tin, and lead.

13. The method of claim 1 , wherein depositing a material that superconducts at or below a critical temperature includes depositing a material that is comprised of at least one material selected from the group consisting of: niobium, and aluminum.

14. The method of claim 1 , wherein depositing a metal layer to overlie the dielectric layer includes depositing a resistive metal layer.

15. The method of claim 14 , wherein depositing a resistive metal layer includes depositing a material that is comprised of platinum.

16. The method of claim 1 , wherein planarizing the metal layer to remove the first portion of the metal layer includes at least one of a mechanical polishing planarization and a chemical-mechanical polishing planarization of the metal.

17. The method of claim 1 , wherein planarizing the metal layer to remove the first portion of the metal layer includes polishing the metal layer to a level even with the upper surface of the dielectric layer.

18. The method of claim 1 , wherein planarizing the metal layer to remove the first portion of the metal layer includes polishing the metal layer to remove substantially all of the first portion of the metal layer.

Assignees

• D Wave Systems Inc

Inventors

• Ladizinsky Eric
• Rose Geordie
• Hilton Jeremy P
• Dantsker Eugene
• Oh Byong Hyop

Classifications

• Y10S977/707

  having different types of nanoscale structures or devices on a common substrate · CPC title

• Y10S977/723

  On an electrically insulating substrate · CPC title

• B82Y10/00 Primary

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• Y10S977/943

  Information storage or retrieval using nanostructure · CPC title

• H01L39/2406

  Electricity · mapped topic