Multi-voltage apparatus for electronics package including magnetic inductor and capacitor and manufacturing thereof

Patent metadata

Field	Value
Publication number	US-10453705-B2
Application number	US-201815865471-A
Country	US
Kind code	B2
Filing date	Jan 9, 2018
Priority date	Jan 9, 2018
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

Apparatuses and methods including an apparatus for an electronics package are disclosed. According to one embodiment, the apparatus can include one or more magnetic inductors, one or more capacitors positioned one of above or below to the one or more magnetic inductors and a plurality of electrical conductors comprising pillars. The pillars can extend substantially vertically to electrically connect the one or more magnetic inductors and the one or more capacitors to the electronics package and the one or more magnetic inductors, the one or more capacitors and the plurality of conductors are disposed one of above or below the electronics package; and at least one electrical conductor comprising a pillar extending substantially vertically to electrically connect the one or more magnetic inductors and the one or more capacitors.

First claim

The claimed invention is:

1. An apparatus for an electronics package comprising:
one or more magnetic inductors;
one or more capacitors positioned one of above or below to the one or more magnetic inductors and insulated thereform;
a plurality of electrical conductors comprising pillars that extend substantially vertically to electrically connect the one or more magnetic inductors and the one or more capacitors to the electronics package, the one or more capacitors and the plurality of conductors are disposed one of above or below the electronics package; and
at least one electrical conductor comprising a pillar extending substantially vertically to electrically connect only with the one or more magnetic inductors and the one or more capacitors.

2. The apparatus of claim 1 , wherein the least one electrical conductor is electrically connected to a voltage discharge end of the one or more magnetic inductors.

3. The apparatus of claim 1 , wherein at least one of the plurality of electrical conductors is electrically connected to a voltage input end of the one or more magnetic inductors.

4. The apparatus of claim 1 , wherein the one or more magnetic inductors and the one or more capacitors are arranged and electrically connected by the plurality of electrical conductors and the at least one electrical conductor such that each of the one or more magnetic inductors comprise an output voltage filter inductor and each of the one or more capacitors comprise an output voltage filter capacitor.

5. The apparatus of claim 1 , wherein the one or more magnetic inductors and the one or more capacitors are arranged and electrically connected by the plurality of electrical conductors and the at least one electrical conductor such that the one or more capacitors are separated into a first group that comprise output voltage filter capacitors and a second group that comprise input voltage filter capacitors.

6. The apparatus of claim 1 , wherein one or more of the plurality of electrical conductors and the least one electrical conductor are varied by one or more of a position, circuit type and number to suit different dc-dc power converter topologies.

7. The apparatus of claim 1 , wherein the one or more capacitors are positioned one of relatively closer to or relatively further from the electronics package than the one or more magnetic inductors.

8. The apparatus of claim 1 , wherein the one or more capacitors are arranged relative to the one or more inductors to create one o£ an assembly with the one or more capacitors vertically stacked so as to be disposed directly above or below the one or more magnetic inductors or an assembly with the one or more capacitors are offset from the one or more inductors along a major surface of the electronics package.

9. The apparatus of claim 1 , wherein the electronics package comprises a voltage regulator along with at least one or more inductors, one or more capacitors and active circuit components such as semiconductor switches.

10. The apparatus of claim 1 , wherein the apparatus is configured as one or both of a buck converter circuit and a boost converter circuit.

11. An apparatus for an electronics package comprising:
one or more magnetic inductors;
a capacitor array positioned one of above or below the one or more magnetic inductors and insulated thereform; and
a plurality of electrical conductors that electrically connect the one or more magnetic inductors and the capacitor array to the electronics package;
a plurality of electrical conductors comprising pillars that extend substantially vertically to electrically connect one of the one or more magnetic inductors or the one or more capacitors to the electronics package;
wherein the capacitor array is embedded in a package core of the electronics package.

12. The apparatus of claim 11 , wherein at least some or all of the plurality of electrical conductors comprise pads exposed at a top surface thereof and positioned at a package build up layer of the electronics package.

13. The apparatus of claim 11 , wherein one or more capacitors of the capacitor array are electrically connected by one or more of the plurality of electrical conductors to the electronics package to provide filtering for one or more voltage outputs, one or more voltage inputs, or other power rails of the electronics package.

14. The apparatus of claim 11 , wherein the one or more magnetic inductors are embedded in the package core layer.

15. The apparatus of claim 11 , wherein the apparatus is configured as one or both of a buck converter circuit and a boost converter circuit.

16. The apparatus of claim 11 , wherein the capacitor array comprises an interdigitated capacitor array.

Assignees

• Intel Corp

Inventors

• Jain Amit K
• Shekhar Sameer
• Radhakrishnan Kaladhar

Classifications

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W44/501 Primary

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title