Memory device and divided clock correction method thereof

Patent metadata

Field	Value
Publication number	US-10453504-B2
Application number	US-201715689260-A
Country	US
Kind code	B2
Filing date	Aug 29, 2017
Priority date	Sep 26, 2016
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.

First claim

What is claimed is:

1. A memory device comprising:
an internal clock generator that is configured to generate a plurality of internal clock signals by dividing a received clock signal, where each of the internal clock signals has a respective phase that is different from the phases of the other internal clock signals;
a deserializer that is configured to use the internal clock signals to deserialize received serial test data;
a data comparator that is configured to compare reference data with pieces of internal data that correspond to the deserialized serial test data; and
a clock controller that is configured to correct a clock dividing start time point of the received clock signal based on a result of the comparison of the reference data with the pieces of internal data.

2. The memory device of claim 1 , wherein the deserializer comprises a plurality of samplers that are configured to respectively receive the plurality of internal clock signals, and
wherein the plurality of samplers are configured to sample the serial test data based on the respective received internal clock signals to deserialize the serial test data.

3. The memory device of claim 1 , wherein the received clock signal is a data strobe signal.

4. The memory device of claim 1 , wherein the received clock signal is a data-dedicated clock signal.

5. The memory device of claim 1 , wherein the serial test data is a preamble signal that is provided before write data that is to be stored in a memory cell of the memory device is provided from a host.

6. The memory device of claim 5 , wherein the serial test data is received if a time period between a first write command that is provided from the host and a second write command that is provided from the host is longer than a reference time period.

7. The memory device of claim 1 , wherein the serial test data is received if a clock correction command for adjusting the clock dividing start time point of the clock signal of the internal clock generator is provided from the host.

8. The memory device of claim 7 , wherein the serial test data is received through a data pad through which write data is received.

9. The memory device of claim 1 , wherein the serial test data is received through a dedicated pad that is distinguished from a data pad through which write data is received.

10. A method for correcting a clock dividing start time point of a memory device, the method comprising:
receiving, at the memory device, serial test data from a host;
deserializing, at a deserializer of the memory device, the serial test data received from the host using a plurality of internal clock signals that are generated by dividing a clock signal that is received from the host;
comparing, at a data comparator of the memory device, reference data with pieces of internal data that correspond to the deserialized serial test data; and
correcting, at a clock controller of the memory device, the clock dividing start time point of the clock signal based on the comparison of the reference data with the pieces of internal data.

11. The method of claim 10 , wherein the serial test data is a preamble signal that is provided before write data that is to be stored in a memory cell of the memory device is provided from the host.

12. The method of claim 10 , wherein the serial test data is received if a clock correction command that allows the memory device to adjust a clock dividing start time point of the internal clock generator is received from the host.

13. The method of claim 10 , wherein the serial test data is received through a dedicated pad that is distinguished from a data pad through which write data is received.

14. The method of claim 10 , wherein the received clock signal is a data strobe signal.

15. The method of claim 10 , wherein the received clock signal is a data-dedicated clock signal.

16. The memory device of claim 2 , further comprising:
a data aligner that is configured to align samples of the serial test data generated by the plurality of samplers on one or more time points.

17. The method of claim 10 , wherein deserializing the serial test data comprises:
sampling, at a plurality of samplers that respectively receive the plurality of internal clock signals, the serial test data based on the respective received internal clock signals to deserialize the serial test data.

18. The method of claim 17 , further comprising:
aligning samples of the serial test data generated by the plurality of samplers on one or more time points.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Dong-Seok
• Bae Seungjun

Classifications

• H04L7/10

  Arrangements for initial synchronisation · CPC title

• H04L7/0337

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/0807

  concerning mainly a recovery circuit for the reference signal · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title