Emission driver and display device including the same

Patent metadata

Field	Value
Publication number	US-9881689-B2
Application number	US-201514597082-A
Country	US
Kind code	B2
Filing date	Jan 14, 2015
Priority date	Aug 4, 2014
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

An emission driver and a display device having the same are disclosed. In one aspect, the emission driver includes a plurality of stages each configured to output an emission control signal, wherein each of the stages includes first and second driving blocks and a buffer block. The buffer block is configured to selectively output an emission control signal so as to operate in a sequential emission mode or in a simultaneous emission mode, the stages being configured to sequentially output a plurality of the emission control signals in the sequential emission mode and substantially simultaneously output the emission control signals in the simultaneous emission mode. The buffer block is further configured to determine a duration in which the emission control signal has a first voltage level based on an interval between time points when first and second intermediate signals have low voltage levels.

First claim

What is claimed is:

1. An emission driver for a display device, the emission driver comprising a plurality of stages each configured to output an emission control signal,
wherein each of the stages includes:
a first driving block configured to i) receive a first input signal, first and second clock signals, and a first driving signal, and ii) output a first intermediate signal based at least in part on the first input signal and the first driving signal;
a second driving block configured to i) receive a second input signal, the first and second clock signals, and a second driving signal, and ii) output a second intermediate signal based at least in part on the second input signal and the second driving signal; and
a buffer block configured to i) receive the first and second intermediate signals, and ii) output an emission control signal based at least in part on the first and second intermediate signals,

wherein the buffer block is further configured to selectively output the emission control signal so as to operate in a sequential emission mode or in a simultaneous emission mode, wherein the stages are configured to i) sequentially output a plurality of the emission control signals in the sequential emission mode and ii) substantially simultaneously output the emission control signals in the simultaneous emission mode,
wherein the buffer block is further configured to determine a duration in which the emission control signal has a first voltage level based at least in part on an interval between a time point when the first intermediate signal has a low voltage level and a time point when the second intermediate signal has the low voltage level, and
wherein the first driving block includes i) a first input unit configured to transmit the first clock signal to a second node based at least in part on a first node signal configured to be applied to a first node and ii) a stabilizing unit configured to stabilize the first intermediate signal based at least in part on a second node signal and the second clock signal, the second node signal being applied to the second node.

2. The emission driver of claim 1 , wherein the buffer block is further configured to output i) the emission control signal having the first voltage level when the first intermediate signal has the low voltage level and ii) the emission control signal having a second voltage level lower than the first voltage level when the second intermediate signal has the low voltage level.

3. The emission driver of claim 2 , wherein a rising edge of the emission control signal is substantially synchronized with a falling edge of the first intermediate signal, and wherein a falling edge of the emission control signal is substantially synchronized with a falling edge of the second intermediate signal.

4. The emission driver of claim 2 , wherein the first and second driving signals are configured to be maintained to have a high voltage level when the emission driver operates in the sequential emission mode, and wherein the first and second input signals and the first and second clock signals are configured to be maintained to have the high voltage level when the emission driver operates in the simultaneous emission mode.

5. The emission driver of claim 1 , wherein the first driving block further includes:
a second input unit configured to transmit the first input signal to the first node based at least in part on the first clock signal;
a pull-up unit configured to pull up the first intermediate signal based at least in part on the second node signal configured to be applied to the second node;
a pull-down unit configured to pull down the first intermediate signal based at least in part on the first node signal;
a driving controller configured to inactivate the pull-down unit based at least in part on the first driving signal; and
a holding unit configured to maintain the second node signal based at least in part on the first clock signal.

6. The emission driver of claim 5 , wherein the first input unit includes a first transistor having a gate electrode electrically connected to the first node, a source electrode to which the first clock signal is configured to be applied, and a drain electrode electrically connected to the second node,
wherein the second input unit includes a second transistor having a gate electrode to which the first clock signal is configured to be applied, a source electrode to which the first input signal is configured to be applied, and a drain electrode electrically connected to the first node,
wherein the pull-up unit includes a third transistor having a gate electrode electrically connected to the second node, a source electrode to which the first driving signal is configured to be applied, and a drain electrode electrically connected to an output terminal configured to output the first intermediate signal,
wherein the pull-down unit includes a fourth transistor having a gate electrode electrically connected to the first node, a source electrode to which the second clock signal is configured to be applied, and a drain electrode electrically connected to the output terminal,
wherein the driving controller includes a fifth transistor having a gate electrode to which the first driving signal is configured to be applied, a source electrode to which a high DC voltage is configured to be applied, and a drain electrode electrically connected to the first node, and
wherein the holding unit includes a sixth transistor having a gate electrode and a source electrode to which the first clock is configured to be applied, and a drain electrode electrically connected to the second node.

7. The emission driver of claim 5 , wherein the stabilizing unit includes seventh and eighth transistors electrically connected in series,
wherein the seventh transistor includes a gate electrode electrically connected to the second node, a source electrode to which a pull-up voltage of the first intermediate signal is configured to be applied, and a drain electrode electrically connected to a source electrode of the eighth transistor, and
wherein the eighth transistor includes a gate electrode to which the second clock signal is configured to be applied, a source electrode electrically connected to the drain electrode of the seventh transistor, and a drain electrode electrically connected to the first node.

8. The emission driver of claim 1 , wherein the second driving block includes:
a first input unit configured to transmit the second clock signal to a second node based at least in part on a first node signal configured to be applied to a first node;
a second input unit configured to transmit the second input signal to the first node based at least in part on the second clock signal;
a pull-up unit configured to pull up the second intermediate signal based at least in part on a second node signal configured to be applied to the second node;
a pull-down unit configured to pull down the second intermediate signal based at least in part on the first node signal;
a driving controller configured to inactivate the pull-down unit based at least in part on the second driving signal;
a holding unit configured to maintain the second node signal based at least in part on the second clock signal; and
a stabilizing unit configured to stabilize the second intermediate signal based at least in part on the second node signal and the first clock signal.

9. The emission driver of claim 8 , wherein the first input unit includes a first transistor having a gate electrode electrically connected to the first node, a source electrode to which the second clock signal is configured to be applied, and a drain electrode electrically connected to the second node,
wherein the second input unit

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Hae-Yeon
• Chung Bo-Yong
• Kim Na-Young

Classifications

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/0205

  Simultaneous scanning of several lines in flat panels · CPC title