Wear leveling in non-volatile memories

Patent metadata

Field	Value
Publication number	US-10452560-B2
Application number	US-201715627091-A
Country	US
Kind code	B2
Filing date	Jun 19, 2017
Priority date	Jul 14, 2015
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

Systems and methods for wear leveling in non-volatile memories (NVMs) are disclosed. One such system includes a cumulative control state determiner configured to determine a cumulative control state indicative of a state of random mappings between physical block addresses (PBAs) and logical block addresses (LBAs) of an NVM, an access network configured to translate a LBA to a PBA based on the cumulative control state, and a background swap scheduler configured to swap PBAs assigned to preselected LBAs based on a control state. One such method involves determining a cumulative control state indicative of a state of random mappings between physical block addresses (PBAs) and logical block addresses (LBAs) of an NVM, translating a LBA to a PBA based on the cumulative control state, and swapping PBAs assigned to preselected LBAs based on a control state.

First claim

What is claimed is:

1. A non-volatile memory system configured for wear leveling, the system comprising:
a cumulative control state determiner configured to determine a cumulative control state indicative of a state of random mappings between physical block addresses (PBAs) and logical block addresses (LBAs) of a non-volatile memory (NVM);
an access network configured to translate a LBA to a PBA based on the cumulative control state; and
a background swap scheduler configured to swap PBAs assigned to preselected LBAs based on a control state.

2. The system of claim 1 :
wherein the cumulative control state comprises a first cumulative control state and a second cumulative control state;
wherein the control state comprises a first control state and a second control state; and
wherein the second cumulative control state is a function of the first cumulative control state and the second control state.

3. The system of claim 2 , wherein the second cumulative control state comprises switch settings used to achieve a sort of a permutation of the first cumulative control state where the permutation is generated using the second control state.

4. The system of claim 1 , further comprising:
a mapping state generator configured to change from a first memory map to a second memory map after the background swap scheduler swaps a preselected number of PBAs;
wherein the first memory map and the second memory map each comprises a preselected number of PBAs.

5. The system of claim 1 , wherein the background swap scheduler is configured to swap PBAs after a preselected number of accesses of the non-volatile memory of the non-volatile memory system.

6. The system of claim 5 , wherein preselected number of accesses comprises 100 writes of the non-volatile memory.

7. The system of claim 1 , wherein the access network is further configured to:
generate a first PBA candidate from a LBA using a first function;
generate a second PBA candidate from the LBA using a second function; and
select either the first PBA candidate or the second PBA candidate for data access based on information related to a background swap of data stored at the first PBA candidate and a background swap of data stored at the second PBA candidate.

8. The system of claim 7 , wherein at least one of the first function or the second function comprises a function performed by at least one of a multi-stage interconnection network or a block cipher.

9. A method for wear leveling in a non-volatile memory system, the method comprising:
determining a cumulative control state indicative of a state of random mappings between physical block addresses (PBAs) and logical block addresses (LBAs) of a non-volatile memory (NVM);
translating a LBA to a PBA based on the cumulative control state; and
swapping PBAs assigned to preselected LBAs based on a control state.

10. The method of claim 9 :
wherein the cumulative control state comprises a first cumulative control state and a second cumulative control state;
wherein the control state comprises a first control state and a second control state; and
wherein the second cumulative control state is a function of the first cumulative control state and the second control state.

11. The method of claim 10 , wherein the second cumulative control state comprises switch settings used to achieve a sort of a permutation of the first cumulative control state where the permutation is generated using the second control state.

12. The method of claim 9 , further comprising:
changing from a first memory map to a second memory map after swapping a preselected number of PBAs;
wherein the first memory map and the second memory map each comprises a preselected number of PBAs.

13. The method of claim 9 , wherein the swapping PBAs assigned to preselected LBAs based on the control state comprises swapping PBAs after a preselected number of accesses of the non-volatile memory of the non-volatile memory system.

14. The method of claim 13 , wherein preselected number of accesses comprises 100 writes of the non-volatile memory.

15. The method of claim 9 , further comprising:
generating a first PBA candidate from a LBA using a first function;
generating a second PBA candidate from the LBA using a second function; and
selecting either the first PBA candidate or the second PBA candidate for data access based on information related to a background swap of data stored at the first PBA candidate and a background swap of data stored at the second PBA candidate.

16. The method of claim 15 , wherein at least one of the first function or the second function comprises a function performed by at least one of a multi-stage interconnection network or a block cipher.

17. A non-volatile memory system configured for wear leveling, the system comprising:
means for determining a cumulative control state indicative of a state of random mappings between physical block addresses (PB As) and logical block addresses (LB As) of a non-volatile memory (NVM);
means for translating a LBA to a PBA based on the cumulative control state; and
means for swapping PBAs assigned to preselected LBAs based on a control state.

18. The system of claim 17 :
wherein the cumulative control state comprises a first cumulative control state and a second cumulative control state;
wherein the control state comprises a first control state and a second control state; and
wherein the second cumulative control state is a function of the first cumulative control state and the second control state.

19. The system of claim 18 , wherein the second cumulative control state comprises switch settings used to achieve a sort of a permutation of the first cumulative control state where the permutation is generated using the second control state.

20. The system of claim 17 , further comprising:
means for changing from a first memory map to a second memory map after swapping a preselected number of PBAs;
wherein the first memory map and the second memory map each comprises a preselected number of PBAs.

21. The system of claim 17 , wherein the means for swapping PBAs assigned to preselected LBAs based on the control state comprises means for swapping PBAs after a preselected number of accesses of [ [a] ] the non-volatile memory of the non-volatile memory system.

22. The system of claim 21 , wherein preselected number of accesses comprises 100 writes of the non-volatile memory.

23. The system of claim 17 , further comprising:
means for generating a first PBA candidate from a LBA using a first function;
means for generating a second PBA candidate from the LBA using a second function; and
means for selecting either the first PBA candidate or the second PBA candidate for data access based on information related to a background swap of data stored at the first PBA candidate and a background swap of data stored at the second PBA candidate.

Assignees

• Western Digital Tech Inc

Inventors

• Gunnam Kiran Kumar

Classifications

• G06F2212/7211

  Wear leveling · CPC title

• G06F2212/152

  Virtualized environment, e.g. logically partitioned system · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F2212/214

  Solid state disk · CPC title