Background reordering—a preventive wear-out control mechanism with limited overhead

Patent metadata

Field	Value
Publication number	US-9268686-B2
Application number	US-201113991338-A
Country	US
Kind code	B2
Filing date	Dec 5, 2011
Priority date	Dec 5, 2011
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

Embodiments of the present disclosure describe background reordering techniques and configurations to prevent wear-out of an integrated circuit device such as a memory device. In one embodiment, a method includes receiving information about one or more incoming access transactions to a memory device from a processor, determining that a wear-leveling operation is to be performed based on a cumulative number of access transactions to the memory device, the cumulative number of access transactions including the one or more incoming access transactions, and performing the wear-leveling operation by mapping a first physical address of the memory device to a second physical address of the memory device based on a pseudo-random mapping function, and copying information from the first physical address to the second physical address. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A method comprising:
receiving information about one or more incoming access transactions to a memory device from a processor;
determining that a wear-leveling operation is to be performed based on a cumulative number of access transactions to the memory device, the cumulative number of access transactions including the one or more incoming access transactions; and
performing the wear-leveling operation by
mapping a first physical address of the memory…

Assignees

• Linkewitsch Niklas
• Intel Corp

Inventors

• Linkewitsch Niklas

Classifications

• G06F3/0619

  Physics · mapped topic

• G06F12/0246 Primary

  Physics · mapped topic

• G06F2212/7211

  Physics · mapped topic

• G06F3/065

  Physics · mapped topic

• G06F3/0679

  Physics · mapped topic