Enhanced re-hosting capability for legacy hardware and software

Patent metadata

Field	Value
Publication number	US-10452111-B2
Application number	US-201816044431-A
Country	US
Kind code	B2
Filing date	Jul 24, 2018
Priority date	Feb 21, 2012
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

Embodiments of the invention are directed toward systems and methods that execute legacy semiconductor applications using a non-legacy controller. In some embodiments a hardware abstraction layer and/or an emulator can be used to provide communication between a non-legacy operating system and legacy components including legacy applications. In some embodiments various methods and/or devices can be used to emulate and/or translate communications between legacy and non-legacy components.

First claim

What is claimed is:

1. A semiconductor process control system comprising:
one or more processors;
a first operating system configured to run on the one or more processors;
a legacy application developed to operate in conjunction with a legacy semiconductor process control system and a legacy operating system different from the first operating system, wherein the legacy application is configured to interact with at least one legacy fabrication tool; and
a hardware abstraction layer and/or emulator layer configured to provide communication between the first operating system and the legacy application;
wherein the hardware abstraction layer and/or emulator layer is configured to emulate the legacy semiconductor process control system on a register-to-register basis, such that the legacy application can be performed on the semiconductor process control system without source code changes to the legacy application.

2. The semiconductor process control system according to claim 1 , wherein the semiconductor process control system is configured to execute previously developed processes and recipes associated with the legacy application without changes to the previously developed processes and recipes.

3. The semiconductor process control system according to claim 1 , wherein the hardware abstraction layer and/or emulator layer is configured to emulate the legacy semiconductor process control system by emulating physical connection points, names, and functions of components associated with the legacy semiconductor process control system.

4. The semiconductor process control system according to claim 1 , wherein the hardware abstraction layer and/or emulator layer is configured to provide timing information to the legacy application.

5. The semiconductor process control system according to claim 1 , wherein the one or more processors include a multicore processor, wherein a first processor core of the multicore processor is configured to emulate the legacy semiconductor process control system, and a second processor core of the multicore processor is configured to control the at least one legacy fabrication tool using the first operating system.

6. The semiconductor process control system according to claim 1 , wherein the hardware abstraction layer and/or emulator layer is further configured to convert between different communication protocols, the different communication protocols including a Peripheral Component Interconnect (PCI) protocol and a Versa Module Europa (VME) protocol.

7. A method for operating a semiconductor process control system, the method comprising:
communicating between a first operating system and a legacy application via a hardware abstraction layer and/or emulator layer, wherein the legacy application is developed to operate in conjunction with a legacy semiconductor process control system and a legacy operating system different from the first operating system;
emulating, by the hardware abstraction layer and/or emulator layer, the legacy semiconductor process control system on a register-to-register basis; and
performing the legacy application on the semiconductor process control system without source code changes to the legacy application.

8. The method of claim 7 , further comprising executing previously developed processes and recipes associated with the legacy application without changes to the previously developed processes and recipes.

9. The method of claim 7 , wherein the hardware abstraction layer and/or emulator layer emulates the legacy semiconductor process control system by emulating physical connection points, names, and functions of components associated with the legacy semiconductor process control system.

10. The method of claim 7 , further comprising providing, by the hardware abstraction layer and/or emulator layer, timing information to the legacy application.

11. The method of claim 7 , further comprising converting, by the hardware abstraction layer and/or emulator layer, between different communication protocols, the different communication protocols including a Peripheral Component Interconnect (PCI) protocol and a Versa Module Europa (VME) protocol.

12. A non-transitory computer readable medium storing instructions that, when executed by a computing device, cause the computing device to perform a method comprising:
communicating between a first operating system and a legacy application via a hardware abstraction layer and/or emulator layer, wherein the legacy application is developed to operate in conjunction with a legacy semiconductor process control system and a legacy operating system different from the first operating system;
emulating, by the hardware abstraction layer and/or emulator layer, the legacy semiconductor process control system on a register-to-register basis; and
performing the legacy application on the legacy semiconductor process control system without source code changes to the legacy application.

13. The non-transitory computer readable medium of claim 12 , further comprising instructions for executing previously developed processes and recipes associated with the legacy application without changes to the previously developed processes and recipes.

14. The non-transitory computer readable medium of claim 12 , further comprising instructions for providing, by the hardware abstraction layer and/or emulator layer, timing information to the legacy application.

15. The non-transitory computer readable medium of claim 12 , further comprising instructions for converting, by the hardware abstraction layer and/or emulator layer, between different communication protocols, the different communication protocols including a Peripheral Component Interconnect (PCI) protocol and a Versa Module Europa (VME) protocol.

Assignees

• Applied Materials Inc

Inventors

• Schauer Ronald Vern
• Covington Mark Roger
• Kumaraswami Suresh
• Puri Amitabh

Classifications

• H02J4/00

  Circuit arrangements for mains or distribution networks not specified as AC or DC; Circuit arrangements for mains or distribution networks combining AC and DC sections or sub-networks (arrangements using intermediate DC-AC-DC conversion H02J1/002; arrangements using high-voltage DC [HVDC] links H02J3/36) · CPC title

• G06F9/45508

  Runtime interpretation or emulation, e g. emulator loops, bytecode interpretation · CPC title

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F13/4063

  Device-to-bus coupling · CPC title

• G06F13/105 Primary

  where the program performs an input/output emulation function · CPC title