Enhanced re-hosting capability for legacy hardware and software

US10037064B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10037064-B2
Application numberUS-201615194270-A
CountryUS
Kind codeB2
Filing dateJun 27, 2016
Priority dateFeb 21, 2012
Publication dateJul 31, 2018
Grant dateJul 31, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Embodiments of the invention are directed toward systems and methods that execute legacy semiconductor applications using a non-legacy controller. In some embodiments a hardware abstraction layer and/or an emulator can be used to provide communication between a non-legacy operating system and legacy components including legacy applications. In some embodiments various methods and/or devices can be used to emulate and/or translate communications between legacy and non-legacy components.

First claim

Opening claim text (preview).

What is claimed is: 1. A power supply system for a semiconductor processing system, the power supply system comprising: an AC adapter configured to convert AC power from an AC power source to DC power; a processing tool adapter electrically coupled a semiconductor processing tool, the processing tool adapter configured to provide power from the AC power source to the semiconductor processing tool; a DC control system adapter electrically coupled to a DC output of the AC adapter and a semiconductor processing control system, wherein the DC control system adapter is configured to provide DC power to the semiconductor processing control system, and wherein the semiconductor processing control system is configured to control the semiconductor processing tool: a DC battery adapter electrically coupled to the DC output of the AC adapter and a battery, the DC battery adapter configured to provide power to the battery; and a power supply control subsystem configured to: monitor DC power drawn by at least one of the DC output of the AC adapter, the processing tool adapter, or the DC control system adapter during a semiconductor process; detect a sustained loss of DC power from the AC adapter based on the monitoring; switch a DC power input of the semiconductor processing control system from the DC control system adapter to the battery to provide DC power to the semiconductor processing control system for saving user data for the semiconductor process; and trigger an orderly shutdown of the semiconductor processing control system, wherein the semiconductor processing control system is configured to, after the DC power from the AC adapter is restored, reload the saved user data for the semiconductor process and resume the semiconductor process based on variables associated with the sustained loss of DC power and the saved user data for the semiconductor process, the variables associated with the sustained loss of DC power determined based on the monitoring. 2. The power supply system of claim 1 , wherein the power supply control subsystem is further configured to control charging of the battery. 3. The power supply system of claim 1 , wherein the power supply control subsystem is configured to: monitor a deviation of the DC power drawn by the DC output of the AC adapter, the processing tool adapter, or the DC control system adapter from a standard power drawn by the corresponding adapter; and determine whether the AC adapter, the processing tool adapter, the DC control system adapter, the semiconductor processing tool, the semiconductor processing control system, or the fan subsystem functions properly, based on the deviation. 4. The power supply system of claim 1 , wherein the power supply control subsystem is configured to monitor a power consumption by at least one of the semiconductor processing tool, the semiconductor processing control system, or the fan subsystem. 5. The power supply system of claim 1 , wherein the power supply control subsystem is configured to monitor temperatures within at least one of the fan subsystem or the semiconductor processing control system. 6. The power supply system of claim 1 , wherein the power supply control subsystem is configured to monitor a fan speed of one or more fans within the fan subsystem. 7. The power supply system of claim 6 , wherein the power supply control subsystem is further configured to turn off the semiconductor processing control system when the fan subsystem fails. 8. The power supply system of claim 1 , wherein the semiconductor processing control system is an external control system. 9. The power supply system of claim 1 , wherein the DC power from the AC adapter includes DC power at two or more different levels. 10. The power supply system of claim 1 , further comprising an uninterruptible power source configured to provide short term power supply to the semiconductor processing control system when the DC power from the AC adapter drops below a threshold level. 11. The power supply system of claim 10 , wherein the uninterruptible power source includes a capacitor bank. 12. The power supply system of claim 10 , wherein the power supply control subsystem comprises a control logic configured to manage a power supply transition between the uninterruptible power source and the DC power from the AC adapter. 13. The power supply system of claim 1 , wherein the power supply control subsystem is further configured to: in response to detecting the sustained loss of the DC power from the AC adapter, send an alert signal to the semiconductor processing control system. 14. The power supply system of claim 1 , wherein the power supply control subsystem comprises a fail-safe logic configured to shut down the power supply system when a system error is detected. 15. The power supply system of claim 1 , wherein the power supply control subsystem comprises a communication adapter communicatively coupled to the semiconductor processing control system for communications between the power supply control subsystem and the semiconductor processing control system. 16. The power supply system of claim 1 , wherein the power supply control subsystem is configured to monitor parameters selected from the list consisting of overall power status, DC bus voltages, DC bus load currents, incoming line parameters, fan temperatures, power supply subsystem temperature, control system temperature, control system CPU core loading, Backplane bus activity, and overall machine state. 17. The power supply system of claim 1 , further comprising: a DC fan adapter electrically coupled to the DC output of the AC adapter and a fan subsystem, the DC fan adapter configured to provide power to the fan subsystem. 18. The power supply system of claim 17 , wherein: the power supply control subsystem is further configured to monitor DC power drawn by the DC fan adapter during the semiconductor process.

Assignees

Inventors

Classifications

  • where the monitored property is the power consumption (power management in a computing system G06F1/3203) · CPC title

  • G06F1/26Primary

    Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

  • electric · CPC title

  • Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

  • Circuit arrangements for mains or distribution networks not specified as AC or DC; Circuit arrangements for mains or distribution networks combining AC and DC sections or sub-networks (arrangements using intermediate DC-AC-DC conversion H02J1/002; arrangements using high-voltage DC [HVDC] links H02J3/36) · CPC title

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What does patent US10037064B2 cover?
Embodiments of the invention are directed toward systems and methods that execute legacy semiconductor applications using a non-legacy controller. In some embodiments a hardware abstraction layer and/or an emulator can be used to provide communication between a non-legacy operating system and legacy components including legacy applications. In some embodiments various methods and/or devices can…
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification G06F1/26. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 31 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).