Apparatus and method for testing a capacitive transducer and/or associated electronic circuitry

Patent metadata

Field	Value
Publication number	US-10451667-B2
Application number	US-201715433613-A
Country	US
Kind code	B2
Filing date	Feb 15, 2017
Priority date	Dec 30, 2008
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

A method of testing a capacitive transducer circuit, for example a MEMS capacitive transducer, by applying a test signal via one or more capacitors provided in the transducer circuit.

First claim

What is claimed is:

1. An integrated circuit for use with a MEMS capacitive transducer having a MEMS capacitor, the integrated circuit comprising:
a biasing node for outputting an output voltage to a first plate of the MEMS capacitor;
a first circuit node for receiving, in a test mode of operation, a test signal from an off-chip test signal generator;
switching circuitry configured to selectively establish, in the test mode of operation, a test signal path between the first circuit node and the biasing node to supply the test signal from said first circuit node to the biasing node;
wherein said test signal path comprises a first capacitor configured such that the test signal is supplied from said first circuit node to the biasing node via the first capacitor.

2. The integrated circuit as claimed in claim 1 , wherein the switching circuitry is operable such that in a non-test mode of operation the biasing node is disconnected from the first circuit node.

3. The integrated circuit as claimed in claim 1 , wherein the switching circuitry is operable such that in the test mode of operation a first plate of the first capacitor is coupled to said biasing node and a second plate of the first capacitor is coupled to said first circuit node.

4. The integrated circuit as claimed in claim 3 , wherein the switching circuitry is operable to selectively couple the second plate of the first capacitor to a reference voltage during a non-test mode of operation, with the first plate of the first capacitor coupled to the biasing node.

5. The integrated circuit as claimed in claim 4 , wherein the switching circuitry is configured such that, in the non-test mode of operation, the first capacitor is connected in parallel with at least a second capacitor.

6. The integrated circuit as claimed in claim 4 , wherein said reference voltage is a non-zero reference voltage.

7. The integrated circuit as claimed in claim 1 , wherein the first circuit node is a first circuit pad or pin.

8. The integrated circuit as claimed in claim 1 , wherein the first circuit node is a dedicated test pin or pad.

9. The integrated circuit as claimed in claim 1 , wherein, in the non-test mode of operation, the first circuit node is connected to a different signal path for input or output of non-test signals.

10. The integrated circuit as claimed in claim 1 , wherein the test signal path further comprises a digital-to-analogue converter located between the first circuit node and the first capacitor.

11. The integrated circuit as claimed in claim 1 , wherein the switching circuitry is controlled in the test or non-test mode of operation in response to a test control signal.

12. The integrated circuit as claimed in claim 11 , wherein the test control signal is received from an off-chip controller.

13. The integrated circuit as claimed in claim 1 , comprising a charge pump configured to generate said voltage at said biasing node.

14. The apparatus comprising an integrated circuit as claimed in claim 1 , a wherein said MEMS capacitive transducer is connected to said biasing node.

15. The apparatus as claimed in claim 14 , wherein said MEMS capacitive transducer is integrated as part of the integrated circuit.

16. The electronic device comprising an integrated circuit as claimed in claim 1 , wherein said electronic device is at least one of: a consumer device; a medical device; an automotive device; a portable device; an audio player; a laptop; a mobile telephone; and a computing device.

17. An integrated circuit, comprising:
a biasing node for supplying a bias voltage to a MEMS capacitive transducer;
a first capacitor having a first plate and a second plate, wherein said first plate of said first capacitor is electrically connected to said biasing node; and
switch circuitry electrically connected to said second plate of said first capacitor, wherein said switch circuitry is operable:
in a test mode of operation to electrically couple said second plate of said first capacitor to a test node for receiving a test signal generated externally from the integrated circuit; and
in a non-test mode to disconnect the first capacitor from the test node.

18. The integrated circuit as claimed in claim 17 , wherein the switch circuitry is operable, in the non-test mode of operation, to electrically connect the second plate of said first capacitor to a reference voltage.

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Steele Colin Findlay
• Pennock John L

Classifications

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• B81C99/004

  during manufacturing · CPC title

• H04R19/005

  using semiconductor materials · CPC title

• H04R2201/003

  Mems transducers or their use · CPC title