Circuit structure

US10448501B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10448501-B2
Application numberUS-201514968021-A
CountryUS
Kind codeB2
Filing dateDec 14, 2015
Priority dateJul 17, 2015
Publication dateOct 15, 2019
Grant dateOct 15, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A circuit structure includes an annular conductor, a conductive via and at least one extension conductor. The annular conductor extends along a direction. The conductive via is disposed in the annular conductor and extending along the direction. The at least one extension conductor is electrically connected to at least one end of the annular conductor and extending toward the conductive via.

First claim

Opening claim text (preview).

What is claimed is: 1. A circuit structure, comprising: an annular conductor extending along a direction; a core substrate penetrated by the annular conductor; a conductive via disposed in the annular conductor and extending along the direction; at least one extension conductor electrically connected to at least one end of the annular conductor and extending toward the conductive via; at least one conductive layer electrically connected to the at least one extension conductor; and at least one conductive line disposed on the core substrate, the at least one conductive line electrically connected to at least one end of the conductive via and electrically insulated from the annular conductor, the at least one conductive layer and the at least one extension conductor; wherein an orthogonal projection of the at least one extension conductor on the core substrate and an orthogonal projection of the at least one conductive line on the core substrate are partially overlapped with each other; wherein a height of the at least one extension conductor from at least one surface of the core substrate is less than a height of the conductive via from the at least one surface of the core substrate. 2. The circuit structure according to claim 1 , wherein the at least one extension conductor is electrically insulated from the conductive via. 3. The circuit structure according to claim 1 , wherein the at least one extension conductor is electrically connected to the conductive via. 4. The circuit structure according to claim 1 , further comprising a dielectric element disposed between the conductive via and the annular conductor. 5. The circuit structure according to claim 4 , wherein a dielectric constant of the dielectric element is from 1 to 6. 6. The circuit structure according to claim 1 , wherein the at least one extension conductor and the annular conductor are electrically connected to a reference potential. 7. The circuit structure according to claim 1 , further comprising: at least one insulating layer disposed on the core substrate, and the at least one conductive line disposed on the at least one insulating layer. 8. A circuit structure, comprising: a conductive via extending along a direction; a first arcuate conductor disposed at one side of the conductive via, and the first arcuate conductor electrically insulated from the conductive via; a core substrate penetrated by the first arcuate conductor; at least one extension conductor electrically connected to at least one end of the first arcuate conductor and extending toward the conductive via; at least one conductive layer electrically connected to the at least one extension conductor; and at least one conductive line disposed on the core substrate, the at least one conductive line electrically connected to at least one end of the conductive via and electrically insulated from the first arcuate conductor, the at least one conductive layer and the at least one extension conductor; wherein an orthogonal projection of the at least one extension conductor on the core substrate and an orthogonal projection of the at least one conductive line on the core substrate are partially overlapped with each other; wherein a height of the at least one extension conductor from at least one surface of the core substrate is less than a height of the conductive via from the at least one surface of the core substrate. 9. The circuit structure according to claim 8 , wherein the at least one extension conductor is electrically insulated from the conductive via. 10. The circuit structure according to claim 8 , wherein the at least one extension conductor is electrically connected to the conductive via. 11. The circuit structure according to claim 8 , further comprising a second arcuate conductor disposed at another side of the conductive via, and the second arcuate conductor electrically insulated from the first arcuate conductor. 12. The circuit structure according to claim 8 , further comprising a dielectric element surrounding the conductive via, the conductive via having two ends that are opposite to each other and exposed, and the dielectric element located between the conductive via and the first arcuate conductor. 13. The circuit structure according to claim 12 , wherein a dielectric constant of the dielectric element is from 1 to 6. 14. The circuit structure according to claim 8 , wherein the first arcuate conductor and the at least one extension conductor are electrically connected to a reference potential. 15. The circuit structure according to claim 8 , wherein the at least one conductive layer is disposed on the at least one surface of the core substrate, and the at least one conductive layer is electrically connected to at least one end of the first arcuate conductor and the at least one extension conductor. 16. The circuit structure according to claim 15 , wherein the at least one conductive layer comprises a first conductive layer and a second conductive layer, the first conductive layer is disposed on the at least one surface of the core substrate, and the second conductive layer is disposed on a part of the first conductive layer. 17. The circuit structure according to claim 8 , further comprising: at least one insulating layer disposed on the core substrate, and the at least one conductive line disposed on the at least one insulating layer. 18. The circuit structure according to claim 1 , wherein the at least one conductive layer is disposed on the at least one surface of the core substrate, and the at least one conductive layer is electrically connected to the at least one end of the annular conductor. 19. The circuit structure according to claim 18 , wherein the at least one conductive layer comprises a first conductive layer and a second conductive layer, the first conductive layer is disposed on the at least one surface of the core substrate, and the second conductive layer is disposed on a part of the first conductive layer.

Assignees

Inventors

Classifications

  • Plated through-holes or plated blind vias filled with insulating material · CPC title

  • Buried plated through-holes, i.e. plated through-holes formed in a core before lamination · CPC title

  • H05K1/0251Primary

    related to vias or transitions between vias and transmission lines · CPC title

  • Metal filled via · CPC title

  • characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated · CPC title

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Frequently asked questions

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What does patent US10448501B2 cover?
A circuit structure includes an annular conductor, a conductive via and at least one extension conductor. The annular conductor extends along a direction. The conductive via is disposed in the annular conductor and extending along the direction. The at least one extension conductor is electrically connected to at least one end of the annular conductor and extending toward the conductive via.
Who is the assignee on this patent?
Ind Tech Res Inst
What technology area does this patent fall under?
Primary CPC classification H05K1/0251. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 15 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).