System and method for an oversampled data converter

Patent metadata

Field	Value
Publication number	US-10447294-B2
Application number	US-201715608807-A
Country	US
Kind code	B2
Filing date	May 30, 2017
Priority date	May 30, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

In accordance with an embodiment, a circuit includes a first oscillator having an oscillation frequency dependent on an input signal at a first input, where the first oscillator is configured to oscillate when an enable input is in a first state and freeze its phase or reduce its frequency when the enable input is in a second state. The circuit also includes a first time-to-digital converter having an input coupled to an output of the first oscillator, and a pulse generator having an input coupled to a first clock input of the circuit and an output coupled to the enable input of the first oscillator, where the pulse generator is configured to produce a pulse having pulse width less than a period of a clock signal at the first clock input.

First claim

What is claimed is:

1. A circuit comprising:
a first oscillator having an oscillation frequency dependent on an input signal at a first input, wherein the first oscillator is configured to oscillate when an enable input is in a first state and freeze its phase when the enable input is in a second state, a present phase of the first oscillator is configured to be stored when the first oscillator freezes its phase, and the first oscillator is configured to resume operation at substantially its previously stored phase;
a first time-to-digital converter having an input coupled to an output of the first oscillator; and
a pulse generator having an input coupled to a first clock input of the circuit and an output coupled to the enable input of the first oscillator, wherein the pulse generator is configured to produce a pulse having pulse width less than a period of a clock signal at the first clock input.

2. The circuit of claim 1 , wherein the first time-to-digital converter comprises a counter having a clock input coupled to the output of the first oscillator.

3. The circuit of claim 1 , further comprising an oscillator-based integrator stage, the oscillator-based integrator stage comprising:
a digitally controlled oscillator (DCO) having a frequency control input coupled to the output of the first time-to-digital converter; and
a second time-to-digital converter having an input coupled to an output of the DCO.

4. The circuit of claim 3 , wherein the DCO further comprises an enable input coupled to the output of the pulse generator, and the DCO is configured to oscillate when the enable input is in the first state and freeze its phase when the enable input is in the second state.

5. The circuit of claim 1 , further comprising:
a feedback counter;
a subtraction circuit having a first input coupled to an output of the first time-to-digital converter, and a second input coupled to an output of the feedback counter; and
a comparator having an input coupled to the output of the feedback counter and an output coupled to an up/down selection input of the feedback counter.

6. The circuit of claim 1 , wherein the pulse generator comprises:
a second oscillator;
a counter having an input coupled to an output of the second oscillator and a reset input coupled to the first clock input of the circuit; and
a comparator coupled to an output of the counter.

7. The circuit of claim 1 , wherein the pulse generator comprises:
a flip-flop having a set input coupled to the first clock input of the circuit; and
a delay circuit coupled between an output of the flip-flop and a reset input of the flip-flop.

8. The circuit of claim 1 , wherein the first oscillator comprises a ring oscillator, the ring oscillator comprising a plurality of stages, wherein each stage of the plurality of stages comprises an inverter and a switch coupled between a supply terminal of the inverter and a power supply node, and the switch comprises an control node coupled to the enable input of the first oscillator.

9. The circuit of claim 1 , wherein the first oscillator comprises a relaxation oscillator.

10. A method of operating a circuit, the method comprising:
receiving an input signal;
enabling a first oscillator for a first period of time upon receiving an edge transition of a clock signal, wherein the first period of time is less than a period of the clock signal, and the first oscillator produces an oscillation signal having a frequency based on the input signal;
counting a number of oscillations of the oscillation signal after receiving the edge transition of the clock signal; and
freezing the first oscillator at an end of the first period of time, wherein freezing the first oscillator comprises storing a present phase of the first oscillator when the first oscillator freezes its phase, and the first oscillator is configured to resume operation at substantially its previously stored phase when the first oscillator is enabled.

11. The method of claim 10 , wherein receiving the input signal comprises receiving the input signal from a microphone.

12. The method of claim 10 , wherein enabling the first oscillator for the first period of time further comprises producing a pulse having a pulse width of the first period of time upon receiving the edge transition of the clock signal, and applying the pulse to an enable input of the first oscillator.

13. The method of claim 10 , further comprising applying the counted number of oscillations to n−1 oscillator-based integrator-based stages coupled in series with the first oscillator, wherein each oscillator-based integrator-based stage comprises a digital input port, a digital output port, a frequency controllable oscillator configured to have a frequency proportional to value of the digital input port, and a time-to-digital converter having a clock input coupled to an output of the frequency controllable oscillator and an output coupled to the digital output port, wherein n is an integer greater than or equal to two.

14. The method of claim 13 , further comprising:
comparing the counted number of oscillations with a first threshold;
incrementing a feedback counter based on the comparing; and
subtracting a value of the feedback counter from the counted number of oscillations.

15. The method of claim 14 , further comprising producing a bitstream based on the comparing, wherein the bitstream comprises an oversampled digital representation of the received input signal.

16. A circuit comprising:
a pulse generator having an input coupled to a clock input of the circuit, wherein the pulse generator is configured to produce a pulse having a pulse width less than a period of a clock signal at the clock input; and
a plurality of oscillator-based integrator stages coupled in series, wherein each oscillator-based integrator-based stage comprises an oscillator and a phase reference integrator coupled to an output of the oscillator, and the oscillator of at least one of the plurality of oscillator-based integrator stages is configured to freeze its phase according to the pulse produced by the pulse generator, a present phase of the oscillator is configured to be stored when the oscillator freezes its phase, and the oscillator is configured to resume operation at substantially its previously stored phase.

17. The circuit of claim 16 , further comprising a comparison circuit having an input coupled to a last stage of the plurality of oscillator-based integrator stages and an output coupled to the phase reference integrator of each of the plurality of oscillator-based integrator stages.

18. The circuit of claim 17 , further comprising a decimation filter coupled to the output of the comparison circuit.

19. The circuit of claim 17 , further comprising a MEMS sensor having an output coupled to an input of a first stage of the plurality of oscillator-based integrator stages.

20. The circuit of claim 19 , wherein the MEMS sensor is a MEMS microphone.

21. The circuit of claim 16 , wherein the pulse generator and the plurality of oscillator-based integrator stages are disposed on a semiconductor substrate.

22. A circuit comprising:
a first oscillator having an oscillation frequency dependent on an input signal at a first input, wherein the first oscillator is configured to oscillate when an enable input is in a first state and to oscillate at a reduced frequency when the enable input is in a second state, wherein the reduced frequency is greater than zero;
a first time-to-digital

Assignees

• Infineon Technologies Austria Ag

Inventors

• Buffa Cesare
• Cardes Garcia Fernando
• Hernandez-Corporales Luis
• Quintero Alonso Andrés
• Wiesbauer Andreas

Classifications

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title

• H03M3/438

  the modulator having a higher order loop filter in the feedforward path · CPC title

• H03M3/39 Primary

  Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators (of digital delta-sigma modulators H03M7/3004) · CPC title

• H03M3/496 Primary

  Details of sampling arrangements or methods · CPC title

• H03M1/60 Primary

  with intermediate conversion to frequency of pulses · CPC title