Analogue-to-digital converter

Patent metadata

Field	Value
Publication number	US-9425813-B2
Application number	US-201514931332-A
Country	US
Kind code	B2
Filing date	Nov 3, 2015
Priority date	Nov 4, 2014
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter ( 201 ) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator ( 401 ) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter ( 202 ) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator ( 403 ). A gain allocation block ( 204 ) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block ( 204 ) may have a second PWM-to-digital modulator ( 203 ) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator ( 403 ).

First claim

The invention claimed is:

1. An analogue-to-digital converter for converting an analogue input signal into a corresponding digital output signal comprising:
a first converter for receiving said analogue input signal and outputting a pulse-width-modulated (PWM) signal based on said analogue input signal and a first conversion gain setting, said first converter comprising a PWM modulator for generating said PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time,
a second converter for receiving said PWM signal and outputting said digital output signal based on said PWM signal and a second conversion gain setting, said second converter comprising a first PWM-to-digital modulator; and
a gain allocation block for generating said first and second conversion gain settings based on said PWM signal.

2. An analogue to digital converter as claimed in claim 1 wherein said gain allocation block comprises a second PWM-to-digital modulator configured to receive a version of said PWM signal and output a control digital signal based on said PWM signal and a controller for receiving said control digital signal to control said first and second conversion gain settings.

3. An analogue to digital converter as claimed in claim 2 wherein said second PWM-to-digital modulator has at least one of a lower output resolution and a lower latency than said first PWM-to-digital modulator.

4. An analogue to digital converter as claimed in claim 2 wherein the second PWM-to-digital modulator comprises a first counter configured to receive a first clock signal and determine a count of the number of periods of the first clock signal during an interval defined by one or more pulses of the PWM signal.

5. An analogue to digital converter as claimed in claim 4 wherein the second PWM-to-digital modulator further comprises a second counter, wherein the first counter is configured to determine a first count of the number of periods of the first clock signal during an interval of a first state of the PWM signal and the second counter is configured to determine a second count of the number of periods of the first clock signal during an interval of a second state of the PWM signal and the second PWM-to-digital modulator is configured to determine a duty-cycle value from said first and second counts.

6. An analogue to digital converter as claimed in claim 2 wherein the controller of the gain allocation block comprises an envelope detector for receiving the digital control signal determining an envelope value.

7. An analogue to digital converter as claimed in claim 6 wherein the gain allocation block comprises a digital gain element for applying a gain based on a third gain setting to the digital control signal prior to the envelope detector.

8. An analogue to digital converter as claimed in claim 2 , the analogue to digital converter being operable in first and second mode, wherein:
in the first mode said a second converter outputs said digital output signal based on the PWM signal; and
in the second mode the second converter is inactive and an activity controller is responsive to the digital control signal produced by the second PWM-to-digital modulator to determine whether to switch to the first mode of operation.

9. An analogue to digital converter as claimed in claim 1 wherein the PWM modulator comprises a comparator for comparing a signal based on the input signal with a periodic time varying reference waveform of fixed frequency.

10. An analogue to digital converter as claimed in claim 9 wherein the excursion of said periodic time varying reference waveform is variable based on said first conversion gain setting.

11. An analogue to digital converter as claimed in claim 9 wherein said PWM modulator is configured to output a first signal level from the start of a duty cycle until the output of the comparator indicates that the periodic time varying reference waveform has reached the same value as the signal based on the input signal and then to output a second signal level until the end of the duty cycle.

12. An analogue to digital converter as claimed in claim 9 wherein said PWM modulator comprises a spike generator configured to output a first signal level from the start of a duty cycle until the output of the comparator indicates that the periodic time varying reference waveform has reached the same value as the signal based on the input signal and then to output a pulse of fixed duration.

13. An analogue to digital converter as claimed in claim 1 wherein said PWM modulator comprises a spike encoder configured to compare an error signal based on the input signal with a reference value and to output a pulse of fixed duration when said error signal reaches said reference value.

14. An analogue to digital converter as claimed in claim 1 wherein said PWM modulator comprises a hysteric comparator configured to a signal based on the input signal to first and second limits and the switch between first and second output states when the first limit is reached and switch between second and first output states when the second limit is reached.

15. An analogue to digital converter as claimed in claim 1 wherein the first PWM-to-digital modulator comprises a controlled oscillator configured to output an oscillation signal at a first frequency during a pulse of the PWM signal.

16. An analogue to digital converter as claimed in claim 15 wherein the controlled oscillator is configured to output the oscillation signal at a second, different frequency, between pulses of the PWM signal.

17. An analogue to digital converter as claimed in claim 15 wherein the first PWM-to-digital modulator comprises a counter configured to count the number of oscillations of the oscillation signal in a count period and a signal processing module for converting the output of the counter to the digital output signal.

18. An apparatus comprising an analogue to digital converter as claimed in claim 1 and a transducer, wherein said analogue input signal for the analogue to digital converter is generated by said transducer.

19. An electronic device comprising an analogue to digital converter as claimed in claim 1 wherein said device is at least one of: a portable device; a battery powered device; a communications device; a mobile or cellular telephone; a personal media device; a computing device; a laptop, notebook or tablet computer; a gaming device; a wearable device.

20. An analogue to digital converter comprising:
a first converter for converting an input analogue signal to a PWM signal;
a second converter for converting the PWM signal to a digital signal; and
a gain allocation block for controlling an analogue gain of the first converter and a digital gain of the second converter;
wherein the gain allocation block is configured to control said analogue gain and said digital gain based on the PWM signal.

21. An analogue to digital converter for converting an analogue input signal into a corresponding digital output signal comprising:
a time encoding block for converting said analogue input signal to a PWM signal with a first conversion gain;
a time decoding block for converting the PWM signal to said digital output signal with a second conversion gain; and
a gain allocation block coupled to an output of the time encoding block to receive a version of the PWM signal and configured to control said first and second conversion gains based on the received PWM signal.

Assignees

• Cirrus Logic Int Semiconductor Ltd

Inventors

• Lesso John Paul
• Hardy Emmanuel Philippe Christian

Classifications

• H03M1/504

  using pulse width modulation · CPC title

• H03M1/18 Primary

  Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging · CPC title

• H03M3/484

  by adapting the gain of the feedback signal, e.g. by adapting the reference values of the digital/analogue converter in the feedback path · CPC title

• H03M1/181 Primary

  in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values · CPC title

• H03K9/08

  of duration- or width-mudulated pulses {or of duty-cycle modulated pulses} · CPC title