Apparatus and method for improving efficiency of power amplifier

Patent metadata

Field	Value
Publication number	US-10447209-B2
Application number	US-201715515491-A
Country	US
Kind code	B2
Filing date	Jan 26, 2017
Priority date	Jan 26, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

Embodiments of the disclosure generally relate to a method and device for improving the efficiency of a power amplifier. The apparatus comprising: a harmonic generator, configured to generate one or more harmonic according to an output signal of a power amplifier; a harmonic feedback device, configured to inject the harmonic generated by the harmonic generator to an input terminal of the power amplifier; and a harmonic eliminator, configured to eliminate the harmonic in the output signal of the power amplifier. According to embodiments of the disclosure, the efficiency of power amplifier can be improved without degrading the linearity.

First claim

What is claimed is:

1. An apparatus, the apparatus comprising:
a harmonic generator, configured to generate even order harmonic according to an output signal of a power amplifier, wherein the harmonic generator comprises:
a harmonic generating device, configured to generate odd order harmonic and the even order harmonic according to the output signal of the power amplifier;
an output match network, configured to open the even order harmonic and to short the odd order harmonic at an output terminal of the power amplifier; and
an input matching network, configured to open the even order harmonic and to short the odd order harmonic at an input terminal of the power amplifier;

a harmonic feedback device, configured to inject the even order harmonic generated by the harmonic generator to the input terminal of the power amplifier; and
a harmonic eliminator, configured to eliminate the even order harmonic in the output signal of the power amplifier.

2. The apparatus according to claim 1 , wherein,
the harmonic generating device comprises a nonlinear variable capacitor,
the harmonic feedback device comprises a linear capacitor,
the harmonic generating device is shunt to ground at the output terminal of the power amplifier,
the harmonic feedback device couples a gate and a drain of a power transistor of the power amplifier.

3. The apparatus according to claim 1 , wherein,
the harmonic generator comprises a nonlinear capacitor Cds between a drain and a source of a power transistor of the power amplifier; and
the harmonic feedback device comprises a capacitor Cgd between a gate and the drain of the power transistor of the power amplifier; and
the harmonic eliminator comprises a differential to single end network.

4. The apparatus according to claim 1 , wherein the power amplifier is a Doherty amplifier, and the apparatus further comprises:
an impedance tuner controller, configured to generate a controlling signal according to power envelope of an input signal of the Doherty power amplifier;
an impedance tuner, configured to connect to output terminal of a carrier amplifier of the Doherty power amplifier, and an impedance of the impedance tuner is tuned according to the controlling signal; and
a timing alignment device, configured to compensate delay between the input signal and the controlling signal.

5. The apparatus according to claim 4 , wherein, the impedance tuner controller comprises:
a power detector, configured to detect a level of the power;
a waveform shaping device, configured to generate a waveform of the controlling signal according to the level of the power; and
a tuner driver amplifier, configured to amplify the waveform and output the amplified controlling signal to the impedance tuner.

6. The apparatus according to claim 5 , wherein,
a bandwidth of the tuner driver amplifier is at least 3 times of that of the power envelope of the input signal.

7. The apparatus according to claim 6 , wherein,
the impedance tuner comprises at least one varactor stack,
an impedance of the impedance tuner is tuned by adjusting a ratio of a reactance and a resistance of the varactor stack.

8. The apparatus according to claim 4 , wherein,
the impedance tuner is arranged in series with the carrier amplifier, the position of the impedance tuner is arranged in one of following three types:
a pre-tuning type, wherein a placement order is the carrier amplifier, the impedance tuner and an output matching network;
a post-tuning type, wherein the order is the carrier amplifier, the output matching network and the impedance tuner;
an integrated tuning type, wherein the impedance tuner is incorporated into the elements of the output matching network.

9. The apparatus according to claim 4 , wherein,
when power level of an output of the power amplifier is lower than a 1st threshold, the impedance of the impedance tuner is fixed at a first static value;
when power level of the output of the power amplifier is higher than the 1st threshold and lower than a second threshold, the impedance of the impedance tuner is dynamically adjusted by the controlling signal according to optimum load impedance trajectory based on load pull measurements;
when power level of the output of the power amplifier enters Doherty operation, the impedance of the impedance tuner is fixed at a second static value;
when power level of the output of the power amplifier reaches a third threshold, the Doherty operation finishes and reach the maximum output power.

10. A method implemented at an apparatus, the method comprising:
generating even order harmonic according to an output signal of a power amplifier, wherein generating the even order harmonic comprises:
generating odd order harmonic and the even order harmonic according to the output signal of the power amplifier;
opening the even order harmonic and shorting the odd order harmonic at an output terminal of the power amplifier; and
opening the even order harmonic and shorting the odd order harmonic at an input terminal of the power amplifier;

injecting the even order harmonic to the input terminal of the power amplifier; and
eliminating the even order harmonic in the output signal of the power amplifier.

11. The method according to claim 10 , wherein,
generating the odd order harmonic and the even order harmonic by using at least one nonlinear variable capacitor; and
injecting the generated harmonic by using linear capacitor.

12. The method according to claim 10 , wherein, the power amplifier is a Doherty power amplifier,
the method further comprises:
generating a controlling signal according to power envelope of an input signal of the Doherty power amplifier;
tuning an impedance of an impedance tuner according to the controlling signal dynamically; and
compensating delay between the input signal and the controlling signal.

13. The method according to claim 12 , wherein, generating controlling signal comprises:
detecting a level of the power;
generating a waveform of the controlling signal according to the level of the power;
amplifying the waveform and outputting the amplified controlling signal to the impedance tuner.

14. The method according to claim 12 , wherein,
the impedance tuner comprises varactor stack,
an impedance of the impedance tuner is tuned by adjusting a ratio of a reactance and a resistance of the varactor stack.

15. The method according to claim 12 , wherein,
when power level of an output of the power amplifier is lower than a 1st threshold, the impedance of the impedance tuner is fixed at a first static value;
when power level of the output of the power amplifier is higher than the 1st threshold and lower than the 2nd threshold, the impedance of the impedance tuner is adjusted by the controlling signal according to optimum load impedance trajectory based on load pull measurements;
when power level of the output of the power amplifier enters Doherty operation, the impedance of the impedance tuner is fixed at a second static value;
when power level of the output of the power amplifier reaches a third threshold, the Doherty operation finishes and reach the maximum output power.

Assignees

• Ericsson Telefon Ab L M

Inventors

• Wang Zhancang

Classifications

• H03F1/38

  Positive-feedback circuit arrangements without negative feedback · CPC title

• H03F2200/387

  A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier · CPC title

• H03F2203/21103

  An impedance adaptation circuit being added at the input of a power amplifier stage · CPC title

• H03F3/213

  in integrated circuits · CPC title

• H03F2200/222

  A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier · CPC title