Device structures for a silicon-on-insulator substrate with a high-resistance handle wafer

Patent metadata

Field	Value
Publication number	US-10446644-B2
Application number	US-201514745704-A
Country	US
Kind code	B2
Filing date	Jun 22, 2015
Priority date	Jun 22, 2015
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

Methods for forming a device structure and device structures using a silicon-on-insulator substrate that includes a high-resistance handle wafer. A doped region is formed in the high-resistance handle wafer. A first trench is formed that extends through a device layer and a buried insulator layer of the silicon-on-insulator substrate to the high-resistance handle wafer. The doped region includes lateral extension of the doped region extending laterally of the first trench. A semiconductor layer is epitaxially grown within the first trench, and a device structure is formed using at least a portion of the semiconductor layer. A second trench is formed that extends through the device layer and the buried insulator layer to the lateral extension of the doped region, and a conductive plug is formed in the second trench. The doped region and the plug comprise a body contact.

First claim

What is claimed is:

1. A method of forming a device structure using a silicon-on-insulator substrate that includes a handle wafer, the method comprising:
forming a first trench isolation region in a device layer of the silicon-on-insulator substrate;
implanting ions through the first trench isolation region and a buried insulator layer of the silicon-on-insulator substrate into a portion of the handle wafer to form a doped region in the handle wafer;
after implanting the ions, forming a first trench extending through the first trench isolation region in the device layer and the buried insulator layer to a top surface of the handle wafer and the doped region, the doped region having a lateral extension extending laterally of the first trench;
epitaxially growing a semiconductor layer within the first trench;
forming a first device structure using at least a portion of the semiconductor layer;
after forming the first device structure, forming a second trench extending through the first trench isolation region and the buried insulator layer to the lateral extension of the doped region; and
forming a conductive plug in the second trench,
wherein the doped region is coupled with the conductive plug to provide a conductive path to the lateral extension.

2. The method of claim 1 wherein the semiconductor layer has a higher dopant concentration proximate to the handle wafer than proximate to a top surface of the device layer.

3. The method of claim 1 further comprising:
forming a second device structure using the device layer,
wherein the first device structure is a power amplifier.

4. The method of claim 1 wherein forming the conductive plug comprises:
filling the second trench with a conductor.

5. The method of claim 1 further comprising:
forming a base layer on the semiconductor layer; and
forming a second trench isolation region in the semiconductor layer to isolate the base layer from a collector contact region in the semiconductor layer.

6. The method of claim 1 wherein the first trench has a first portion of a first width within the device layer and a portion of the buried insulator layer adjacent to the device layer, the first trench has a second portion of a second width within the buried insulator layer proximate to the handle wafer, and the second width is less than the first width.

7. The method of claim 1 wherein the first trench has a first portion with a first width within the device layer and a portion of the buried insulator layer, the first trench has a second portion with a second width within the buried insulator layer proximate to the handle wafer, and the second width is greater than the first width, and further comprising:
forming a collector contact extending through the device layer and the buried insulator layer to a portion of the semiconductor layer in the second portion of the first trench.

8. The method of claim 1 further comprising:
forming deep trench isolation extending through the device layer and the buried insulator layer into the handle wafer adjacent to the first trench.

9. The method of claim 1 wherein the handle wafer has a resistivity greater than 1 kΩ-cm.

10. The method of claim 1 further comprising:
forming non-conductive spacers on sidewalls of the first trench that extend vertically relative to the top surface of the handle wafer,
wherein the non-conductive spacers are formed before epitaxially growing the semiconductor layer within the first trench.

11. The method of claim 10 wherein at least one of the non-conductive spacers is laterally arranged between the first trench and the second trench.

12. The method of claim 1 wherein the doped region is wider than the first trench.

13. The method of claim 1 wherein the doped region is offset laterally to only one side of the first trench.

14. The method of claim 1 further comprising:
forming a second trench isolation region in the semiconductor layer,
wherein the second trench isolation region extends only partially through a thickness of the semiconductor layer.

15. The method of claim 14 wherein the semiconductor layer has a lower section with a higher dopant concentration proximate to the handle wafer than an upper section proximate to a top surface of the device layer, the second trench isolation region extends fully through the lower section of the semiconductor layer, and the second trench isolation region extends only partially through the lower section of the semiconductor layer.

16. The method of claim 1 wherein forming the first trench extending through the first trench isolation region in the device layer and the buried insulator layer to the top surface of the handle wafer and the doped region comprises:
before epitaxially growing the semiconductor layer within the first trench, forming an upper portion of the first trench within the device layer and a first portion of the buried insulator layer; and
after forming the upper portion of the first trench, forming a lower portion of the first trench extending through a second portion of the buried insulator layer to the top surface of the handle wafer and the doped region,
wherein the lower portion of the first trench has a width that is greater than a width of the upper portion of the first trench.

17. The method of claim 1 wherein forming the first trench extending through the first trench isolation region in the device layer and the buried insulator layer to the top surface of the handle wafer and the doped region comprises:
before epitaxially growing the semiconductor layer within the first trench, forming an upper portion of the first trench within the device layer and a first portion of the buried insulator layer; and
after forming the upper portion of the first trench, forming a lower portion of the first trench extending through a second portion of the buried insulator layer to the top surface of the handle wafer and the doped region,
wherein the lower portion of the first trench has a width that is less than a width of the upper portion of the first trench.

Assignees

• Globalfoundries Inc

Inventors

• Camillo-Castillo Renata
• Ding Hanyi
• Feilchenfeld Natalie B
• Jain Vibhor
• Stamper Anthony K

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title