Semiconductor devices and semiconductor dice including electrically conductive interconnects between die rings

Patent metadata

Field	Value
Publication number	US-10446507-B2
Application number	US-201715691303-A
Country	US
Kind code	B2
Filing date	Aug 30, 2017
Priority date	Aug 30, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A semiconductor device includes a semiconductor die comprising integrated circuitry over a substrate of a semiconductor material. A first die ring comprises one or more electrically conductive materials at least partially surrounding the integrated circuitry, the one or more electrically conductive materials comprising an electrically conductive path from proximate a surface of the substrate to an exposed surface of the semiconductor die. A second die ring comprises an electrically conductive material and is disposed around the first die ring. A first electrically conductive interconnect electrically connects the first die ring and to second die ring. Related semiconductor devices and semiconductor dice are disclosed.

First claim

What is claimed is:

1. A semiconductor device, comprising: a semiconductor die comprising integrated circuitry; a first die ring comprising one or more electrically conductive materials at least partially surrounding the integrated circuitry, the one or more electrically conductive materials comprising an electrically conductive path extending through alternating levels of a conductive material and an insulative material; a second die ring comprising an electrically conductive material disposed around the first die ring; and a third die ring comprising an electrically conductive material disposed around the second die ring, each of the first die ring, the second die ring, and the third die ring coupled to an adjacent die ring by electrically conductive interconnects that are physically spaced from one another, the electrically conductive interconnects extending from a surface of the semiconductor die into the semiconductor die through the alternating levels of the conductive material and the insulative material.

2. The semiconductor device of claim 1 , wherein the first die ring and the second die ring each comprise conductive pads and conductive vias forming the electrically conductive path from proximate a surface of a substrate to the surface of the semiconductor die.

3. The semiconductor device of claim 1 , wherein the first die ring, the second die ring, and the electrically conductive interconnects comprise tungsten.

4. The semiconductor device of claim 1 , wherein the first die ring exhibits a reduced width at a location proximate the electrically conductive interconnects relative to a width thereof distal to the electrically conductive interconnects.

5. The semiconductor device of claim 4 , wherein the reduced width comprises between about fifty percent and about eighty percent of a width of the first die ring at locations of the first die ring distal from the electrically conductive interconnects.

6. The semiconductor device of claim 1 , wherein the third die ring is in electrical communication with the second die ring at least through an electrically conductive interconnect electrically isolated from an electrically conductive interconnect in electrical communication with the second die ring and the first die ring.

7. The semiconductor device of claim 1 , wherein the third die ring comprises a discontinuous segmented structure, different portions of the third die ring electrically coupled to the second die ring with at least one electrically conductive interconnect different from an electrically conductive interconnect electrically connecting the first die ring to the second die ring, at least one portion of the third die ring electrically isolated from at least another portion of the third die ring.

8. The semiconductor device of claim 1 , further comprising a fourth die ring disposed around the third die ring and in electrical communication with the third die ring.

9. The semiconductor device of claim 1 , further comprising a fourth die ring disposed around the third die ring, wherein the third die ring is in electrical communication with the second die ring and comprises a continuous structure around the second die ring, and wherein the fourth die ring is in electrical communication with the third die ring and comprises a continuous structure.

10. The semiconductor device of claim 1 , wherein at least one of the first die ring and the second die ring comprises four edges, wherein each edge of the at least one of the first die ring and the second die ring is electrically connected to at least four electrically conductive interconnects.

11. The semiconductor device of claim 1 , wherein vertical edges of the at least one of the first die ring and the second die ring are electrically connected to a greater number of electrically conductive interconnects than horizontal edges thereof.

12. A semiconductor die, comprising: a first die ring in a peripheral region of a semiconductor die, the first die ring comprising a continuous electrically conductive structure extending from an upper surface of the semiconductor die into the semiconductor die and comprising an electrically conductive material; a second die ring around the first die ring, the second die ring comprising an electrically conductive material; a third die ring around the second die ring; a first electrically conductive interconnect electrically connecting the first die ring to the second die ring, wherein a distance between the first die ring and the second die ring at a location proximate the first electrically conductive interconnect is greater than a distance between the first die ring and the second die ring at a location distal to the first electrically conductive interconnect; and a second electrically conductive interconnect electrically connecting the second die ring and the third die ring and physically separated from the first electrically conductive interconnect.

13. The semiconductor die of claim 12 , wherein the second die ring is electrically connected to the first die ring with electrically conductive interconnects.

14. The semiconductor die of claim 12 , wherein the first die ring is electrically connected to the second die ring with electrically conductive interconnects, wherein vertical edges of the first die ring are electrically coupled to more electrically conductive interconnects than horizontal edges thereof.

15. The semiconductor die of claim 12 , wherein the second die ring comprises a discontinuous segmented structure extending around the first die ring, wherein a first portion of the second die ring and a second portion of the second die ring are electrically connected to the first die ring.

16. The semiconductor die of claim 12 , wherein the first die ring, the second die ring, and the third die ring each comprise a continuous electrically conductive structure.

17. The semiconductor die of claim 12 , wherein the first die ring and the second die ring each comprise a continuous electrically conductive structure and the third die ring comprises a discontinuous segmented electrically conductive structure.

18. The semiconductor die of claim 17 , further comprising a fourth die ring disposed around the third die ring, wherein the fourth die ring is in electrical communication with the first die ring, the second die ring, and the third die ring through at least a third electrically conductive interconnect.

19. The semiconductor die of claim 18 , wherein each of the first die ring, the second die ring, the third die ring, and the fourth die ring each comprise a continuous electrically conductive structure.

20. A semiconductor device, comprising: a first die ring extending around integrated circuitry of a semiconductor die, wherein the first die ring comprises a continuous electrically conductive structure extending around the integrated circuitry; a second die ring comprising an electrically conductive material around the first die ring; a third die ring extending around the second die ring; first electrically conductive interconnects electrically coupling the first die ring to the second die ring; and second electrically conductive interconnects electrically coupling the second die ring to the third die ring and physically separated from the first electrically conductive interconnects.

21. The semiconductor device of claim 20 , wherein the second die ring comprises a discontinuous segmented structure extending around the first die ring.

22. The semiconductor device of claim 20 , wherein the second die ring comprise

Assignees

• Micron Technology Inc

Inventors

• Zhu Hongbin
• Zeng Qinglin
• Osterberg Daniel
• Carlson Merri L
• Haller Gordon A
• Adams Jeremy

Classifications

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W42/00 Primary

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W72/00 Primary

  Interconnections or connectors in packages · CPC title