Packaged integrated circuit having stacked die and method for therefor

Patent metadata

Field	Value
Publication number	US-10446476-B2
Application number	US-201815925022-A
Country	US
Kind code	B2
Filing date	Mar 19, 2018
Priority date	Sep 19, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A packaged integrated circuit (IC) device includes a first IC die with a first inductor, a first layer of adhesive on a first major surface of the first IC die, an isolation layer over the first layer of adhesive, a second layer of adhesive on the isolation layer, a second IC die on the second layer of adhesive, and a second inductor in the second IC die aligned to communicate with the first inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die.

First claim

What is claimed is:

1. A packaged integrated circuit (IC) device comprising:
a first IC die;
a first inductor in the first IC die;
a first layer of adhesive on a first major surface of the first IC die;
an isolation layer over the first layer of adhesive;
a second layer of adhesive on the isolation layer;
a second IC die on the second layer of adhesive, wherein a first major surface of the second IC die is in direct contact with the second layer of adhesive;
a second inductor in the second IC die aligned to communicate with the first inductor, wherein the isolation layer extends beyond a first edge of the second IC die wherein a creepage distance between the first edge of the second IC die and a first edge of the isolation layer is at least 100 micrometers; and
a lead frame flag, wherein the first die is attached to the lead frame flag;
wire bonds between the first IC die and a first set of lead fingers; and
wire bonds between the second IC die and a second set of lead fingers, wherein an end of the wire bonds between the second IC die and the second set of lead fingers are connected to a second major surface of the second die which is opposite the first major surface of the second IC die.

2. The IC device of claim 1 further comprising:
a conductive ring beneath the second layer of adhesive extending past the first edge of the second IC die, wherein the first edge is perpendicular to the second layer of adhesive and the conductive ring.

3. The IC device of claim 1 wherein:
at least one of the first and second adhesive layers is a die attach film.

4. The IC device of claim 1 wherein:
the isolation layer includes material that is one of a group consisting of a dielectric, epoxy, bismaleimide triazine (BT), FR-4, a resin, and a polyimide material.

5. The IC device of claim 2 wherein:
minimum distance between the first edge of the second IC die and a perimeter of the conductive ring extending past the first edge of the second IC die is at least 10 micrometers.

6. The IC device of claim 1 wherein:
one of the first IC die and the second IC die is coupled to a high voltage supply and the other one of the first IC die and the second IC die is coupled to a low voltage supply.

7. The IC device of claim 2 further comprising:
corners of outer perimeter of the conductive ring are rounded.

8. The IC device of claim 2 wherein:
the conductive ring is made of copper and extends around all edges of the second IC die that are perpendicular to the second layer of adhesive and the conductive ring.

9. The IC device of claim 1 wherein:
thickness of the first adhesive layer, the second adhesive layer, and the isolation layer together is at least 5 micrometers.

10. The IC device of claim 1 wherein:
thickness of the first adhesive layer, the second adhesive layer, and the isolation layer together is between 90 and 500 micrometers.

11. The IC device of claim 2 , wherein the conductive ring has an inner perimeter and an outer perimeter, the inner perimeter is beneath the second IC die, and the outer perimeter extends around all four edges of the second IC die, wherein each of the four edges is perpendicular to the second adhesive layer and the conductive ring, such that all corners of the second IC die are over the conductive ring within the outer perimeter.

12. A packaged integrated circuit (IC) device comprising:
a first IC die;
a first inductor in the first IC die;
a first layer of adhesive on a first major surface of the first IC die;
an isolation layer over the first layer of adhesive;
a second layer of adhesive on the isolation layer;
a second IC die on the second layer of adhesive;
a second inductor in the second IC die aligned to communicate with the first inductor, wherein the isolation layer extends beyond a first edge of the second IC die; and
a conductive ring beneath the second layer of adhesive having an inner perimeter and an output perimeter, wherein the inner perimeter is beneath the second IC die, between the first and second IC die, and the outer perimeter extends around all four edges of the second IC die, wherein each of the four edges is perpendicular to the second adhesive layer and the conductive ring, such that all corners of the second IC die are over the conductive ring within the outer perimeter wherein a minimum distance between the first edge of the second IC die and the outer perimeter of the conductive ring extending past the first edge of the second IC die is at least 10 micrometers.

13. The IC device of claim 12 wherein:
the isolation layer includes material that is one of a group consisting of a dielectric, epoxy, bismaleimide triazine (BT), FR-4, a resin, and a polyimide material.

14. The IC device of claim 12 wherein:
creepage distance between the first edge of the second IC die and a first edge of the insulator layer is at least 100 micrometers.

15. The IC device of claim 12 wherein:
one of the first IC die and the second IC die is coupled to a high voltage supply and the other one of the first IC die and the second IC die is coupled to a low voltage supply.

16. The IC device of claim 12 wherein corners of the outer perimeter of the conductive ring are rounded.

17. The IC device of claim 12 wherein the conductive ring is made of copper.

Assignees

• Nxp Usa Inc

Inventors

• Higgins Iii Leo M
• Brauchler Fred T
• Carpenter Burton Jesse
• Liu Jinmei
• Ching Jr Mariano Layson
• Yao Jinzhong
• Pang Xingshou
• Wang Jianhong
• Wei Yadong

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W72/07551

  characterised by changes in properties of the bond wires during the connecting · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title

• H10W72/50

  Bond wires · CPC title