Semiconductor device and method of forming encapsulated wafer level chip scale package (EWLCSP)

Patent metadata

Field	Value
Publication number	US-10446459-B2
Application number	US-201715618343-A
Country	US
Kind code	B2
Filing date	Jun 9, 2017
Priority date	Feb 27, 2014
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A semiconductor device has a semiconductor die and an encapsulant around the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The fan-in interconnect structure includes an insulating layer and a conductive layer formed over the semiconductor die. The conductive layer remains within a footprint of the semiconductor die. A portion of encapsulant is removed from over the semiconductor die. A backside protection layer is formed over a non-active surface of the semiconductor die after depositing the encapsulant. The backside protection layer is formed by screen printing or lamination. The backside protection layer includes an opaque, transparent, or translucent material. The backside protection layer is marked for alignment using a laser. A reconstituted panel including the semiconductor die is singulated through the encapsulant to leave encapsulant disposed over a sidewall of the semiconductor die.

First claim

What is claimed:

1. A semiconductor device, comprising:
a semiconductor die;
an encapsulant deposited around the semiconductor die, wherein the encapsulant is disposed on a side surface of the semiconductor die;
a first insulating layer formed over a first surface of the semiconductor die;
a fan-in interconnect structure formed over the semiconductor die and first insulating layer, wherein the fan-in interconnect structure includes:
(a) a conductive layer formed over the semiconductor die and first insulating layer, and
(b) a second insulating layer formed over the conductive layer, and terminating within a footprint of the semiconductor die; and

a protection layer formed over a top surface of the encapsulant and coplanar with a second surface of the semiconductor die opposite the fan-in interconnect structure.

2. The semiconductor device of claim 1 , wherein the conductive layer and second insulating layer are offset inwards from the side surface of the semiconductor die.

3. The semiconductor device of claim 1 , wherein a thickness of the encapsulant disposed on the side surface of the semiconductor die is less than 100 micrometers.

4. The semiconductor device of claim 3 , wherein the thickness of the encapsulant disposed on the side surface of the semiconductor die ranges from 30 to 50 micrometers.

5. The semiconductor device of claim 1 , wherein a thickness of the encapsulant over the semiconductor die is at least 100 micrometers.

6. The semiconductor device of claim 1 , further including a third insulating layer formed in direct contact with the first insulating layer, wherein the conductive layer is formed over the semiconductor die, first insulating layer, and third insulating layer.

7. The semiconductor device of claim 1 , wherein the protective layer includes a transparent material or translucent material.

8. The semiconductor device of claim 6 , wherein the conductive layer, the second insulating layer and the third insulating layer are offset inwards from the side surface of the semiconductor die.

9. A semiconductor device, comprising:
a semiconductor die;
an encapsulant deposited on a side surface of the semiconductor die;
a first insulating layer formed over a first surface of the semiconductor die;
an interconnect structure formed within a footprint of the semiconductor die and first insulating layer; and
a protection layer formed over a top surface of the encapsulant and over a second surface of the semiconductor die opposite the fan-in interconnect structure.

10. The semiconductor device of claim 9 , wherein the interconnect structure includes:
a conductive layer formed over the semiconductor die and first insulating layer; and
a second insulating layer formed over the conductive layer.

11. The semiconductor device of claim 9 , wherein a thickness of the encapsulant deposited on the side surface of the semiconductor die is less than 100 micrometers.

12. The semiconductor device of claim 11 , wherein the thickness of the encapsulant deposited on the side surface of the semiconductor die ranges from 30 to 50 micrometers.

13. The semiconductor device of claim 9 , wherein a thickness of the encapsulant over the semiconductor die is at least 100 micrometers.

14. The semiconductor device of claim 10 , further including a third insulating layer formed in direct contact with the first insulating layer, wherein the conductive layer is formed over the semiconductor die, first insulating layer, and third insulating layer.

15. A semiconductor device, comprising:
a semiconductor die;
an encapsulant deposited around the semiconductor die, wherein the encapsulant is disposed on a side surface of the semiconductor die;
a fan-in interconnect structure formed over the semiconductor die; and
a protection layer formed over a surface of the encapsulant and over a surface of the semiconductor die opposite the fan-in interconnect structure.

16. The semiconductor device of claim 15 , further including an insulating layer formed over a surface of the semiconductor die.

17. The semiconductor device of claim 15 , wherein the fan-in interconnect structure includes:
a conductive layer formed over the semiconductor die; and
an insulating layer formed over the conductive layer.

18. The semiconductor device of claim 15 , wherein a thickness of the encapsulant disposed on the side surface of the semiconductor die is less than 100 micrometers.

19. The semiconductor device of claim 15 , wherein a thickness of the encapsulant over the semiconductor die is at least 100 micrometers.

Assignees

• Stats Chippac Pte Ltd

Inventors

• Strothmann Thomas J
• Yoon Seung Wook
• Lin Yaojian

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/014

  using batch processing · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/922

  Bond pads being integral with underlying chip-level interconnections · CPC title