Integrated circuit chip with molding compound handler substrate and method

Patent metadata

Field	Value
Publication number	US-10446442-B2
Application number	US-201615386097-A
Country	US
Kind code	B2
Filing date	Dec 21, 2016
Priority date	Dec 21, 2016
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

Disclosed are integrated circuit (IC) chip structures (e.g., radio frequency (RF) IC chip structures) and methods of forming the structures with an electrically insulative molding compound handler substrate. Each structure includes at least: an electrically insulative molding compound handler substrate; an insulator layer on the handler substrate; and one or more semiconductor devices (e.g., RF semiconductor devices) on the insulator layer. Each method includes at least: attaching a temporary carrier above back end of the line (BEOL) metal levels, which are over an interlayer dielectric layer covering one or more semiconductor devices; removing at least a portion of a semiconductor handler substrate, which is below the semiconductor device(s) and separated therefrom by an insulator layer; replacing the semiconductor handler substrate with a replacement handler substrate made of an electrically insulative molding compound; and removing the temporary carrier. The molding compound handler substrate provides backside isolation that prevents unwanted noise coupling.

First claim

What is claimed is:

1. An integrated circuit (IC) chip comprising:
a replacement handler substrate comprising a molding compound, the molding compound being electrically insulative;
an insulator layer having a first surface immediately adjacent to the replacement handler substrate and a second surface opposite the first surface;
at least one semiconductor device on the second surface; and
a semiconductor body immediately adjacent to the first surface,
wherein the semiconductor body comprises any of an additional semiconductor device and a biasable conductive field plate, and
wherein the replacement handler substrate is on the first surface of the insulator layer positioned laterally adjacent to the semiconductor body and further extends over the semiconductor body.

2. The integrated circuit (IC) chip of claim 1 , wherein the molding compound is thermally conductive.

3. The integrated circuit (IC) chip of claim 1 , wherein the molding compound comprises an organic material with filler particles.

4. The integrated circuit (IC) chip of claim 1 , wherein the semiconductor device has a first portion aligned above the semiconductor body and a second portion that extends laterally beyond the semiconductor body such that the semiconductor device is partially offset from the semiconductor body.

5. The integrated circuit (IC) chip of claim 1 ,
wherein the replacement handler substrate comprises:
a first molding compound layer immediately adjacent to the first surface of the insulator layer; and,
a second molding compound layer on the first molding compound layer, and

wherein the integrated circuit (IC) chip further comprises:
a metal device between the first molding compound layer and the second molding compound layer such that a top of the metal device is physically separated from the first surface of the insulator layer by the first molding compound layer and a bottom of the metal device is completely covered by the second molding compound layer; and
a through substrate via extending vertically from the top of the metal device through the first molding compound layer and the insulator layer, wherein the through substrate via enables an electrical connection between the metal device and the semiconductor device.

6. The integrated circuit (IC) chip of claim 5 , further comprising:
an isolation region on the second surface of the insulator layer and positioned laterally adjacent to the semiconductor device;
at least one interlayer dielectric layer over the semiconductor device and the isolation region;
a metal level above the interlayer dielectric layer and comprising a wire; and,
a contact extending vertically from the wire through the interlayer dielectric layer to the semiconductor device, wherein the through substrate via further extends vertically through the isolation region and the interlayer dielectric layer to the wire.

7. The integrated circuit (IC) chip of claim 5 , wherein the metal device comprises any of an inductor, a passive device, and an antenna.

8. A method comprising:
providing a wafer comprising a semiconductor handler substrate, an insulator layer having a first surface immediately adjacent to the semiconductor handler substrate and a second surface opposite the first surface, and a semiconductor layer on the second surface;
forming at least one semiconductor device using the semiconductor layer and further forming a functional semiconductor feature using the semiconductor handler substrate, wherein the functional semiconductor feature comprises any of an additional semiconductor device and a biasable conductive field plate;
forming at least one interlayer dielectric layer over the semiconductor device;
forming metal levels above the interlayer dielectric layer;
attaching a temporary carrier above the metal levels;
patterning the semiconductor handler substrate such that a semiconductor body remains adjacent to the first surface, wherein the semiconductor body comprises the functional semiconductor feature;
replacing a removed portion of the semiconductor handler substrate with a replacement handler substrate, the replacement handler substrate comprising an electrically insulative molding compound that is positioned laterally adjacent to and extends over the semiconductor body; and
removing the temporary carrier.

9. The method of claim 8 , wherein the molding compound is thermally conductive.

10. The method of claim 8 , wherein the molding compound comprises an organic material with filler particles.

11. The method of claim 8 , wherein the patterning is performed such that the semiconductor device has a first portion aligned above the semiconductor body and a second portion that extends laterally beyond the semiconductor body.

12. The method of claim 8 ,
wherein the forming of the functional semiconductor feature comprises forming a capacitor, and
wherein the forming of the capacitor comprises:
forming a trench through the semiconductor layer and the insulator layer and into the semiconductor handler substrate;
forming a doped region for a first conductive field plate in the semiconductor handler substrate adjacent to the trench;
lining the trench with a dielectric layer for a capacitor dielectric; and
filling the trench with a doped semiconductor material for a second conductive field plate.

13. The method of claim 8 , further comprising:
forming at least one through substrate via that extends vertically from a top surface of the interlayer dielectric layer into the semiconductor handler substrate;
during the removing, leaving the through substrate via intact; and,
during the replacing, forming a first molding compound layer immediately adjacent to the first surface of the insulator layer and around the through substrate via and the semiconductor body; forming a metal device on the first molding compound layer opposite the first surface of the insulator layer such that a top of the metal device is physically separated from the first surface of the insulator layer and in contact with the through substrate via, wherein the metal device comprises any of an inductor, a passive device, and an antenna; and forming a second molding compound layer on the first molding compound layer and extending laterally over the metal device such that a bottom of the metal device is completely covered by the second molding compound layer,
wherein the replacement handler substrate comprises the first molding compound layer and the second molding compound layer and contains the metal device, and
wherein the through substrate via enables an electrical connection between the metal device and the semiconductor device.

14. The integrated circuit (IC) chip of claim 1 , further comprising:
an isolation region on the second surface of the insulator layer and positioned laterally adjacent to the semiconductor device;
at least one interlayer dielectric layer over the semiconductor device and the isolation region;
a metal level above the interlayer dielectric layer and comprising a wire;
a contact extending vertically from the wire through the interlayer dielectric layer to the semiconductor device; and
a via extending vertically from the wire through the interlayer dielectric layer, the isolation region and the insulator layer to the semiconductor body.

15. the integrated circuit (IC) chip of claim 1 ,
wherein the additional semiconductor device comprises a capacitor comprising: a first conductive field plate; a second conductive field plate; and a capacitor dielectric between the first conductive field plate and the second conductive field plate,
wherein the first conductive f

Assignees

• Globalfoundries Inc

Inventors

• Butt Shahid A
• Tessler Christopher L

Classifications

• H10P72/7432

  used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W44/248

  for antennas · CPC title

• H10W44/243

  for decoupling, e.g. bypass capacitors · CPC title

• H10W44/241

  for passive devices or passive elements · CPC title