Read circuit for a variable resistance memory device

Patent metadata

Field	Value
Publication number	US-10446227-B2
Application number	US-201815911413-A
Country	US
Kind code	B2
Filing date	Mar 5, 2018
Priority date	Sep 20, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

According to one embodiment, a memory device includes: a memory cell including a variable resistance element and connected between a word line and a bit line; and a control circuit configured to control an operation of the memory cell. The variable resistance element includes: a first layer including a first compound including oxygen; a second layer including a second compound including oxygen; and a third layer between the first layer and the second layer.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell including a variable resistance element and connected between a word line and a bit line;
a control circuit configured to control an operation of the memory cell,
a row control circuit connected to the word line;
a first read circuit connected to the row control circuit;
a column control circuit connected to the bit line; and
a second read circuit connected to the column control circuit,
wherein the variable resistance element includes:
a first layer including a first compound including oxygen;
a second layer including a second compound including oxygen; and
a third layer between the first layer and the second layer, and
wherein at a time of a read operation of data from the memory cell,
the first read circuit is configured to detect a first signal which is output from the memory cell to the word line,
the second read circuit is configured to detect a second signal which is output from the memory cell to the bit line, and
the control circuit is configured to judge the data in the memory cell, based on the first signal and the second signal.

2. The device according to claim 1 , wherein the variable resistance element is configured to have one resistance state among a first resistance state, a second resistance state and a third resistance state in accordance with application of a voltage to the first layer and the second layer.

3. The device according to claim 1 , wherein the first compound is different from the second compound.

4. The device according to claim 1 , wherein the first compound includes nitrogen.

5. The device according to claim 1 , wherein a thickness of the first layer is different from a thickness of the second layer.

6. The device according to claim 1 , wherein each of the first compound and the second compound is at least one selected from the group consisting of titanium oxide, titanium oxynitride, tantalum oxide and tungsten oxide.

7. The device according to claim 1 , wherein a material of the third layer is at least one selected from the group consisting of amorphous silicon, amorphous silicon germanium, amorphous germanium, aluminum oxide, silicon oxide and hafnium oxide.

8. The device according to claim 1 , wherein the variable resistance element further includes:
a first electrode,
a second electrode, and
a stacked body disposed between the first electrode and the second electrode, the stacked body including the first layer, the second layer and the third layer.

9. A memory device comprising:
a memory cell including a variable resistance element and connected between a word line and a bit line;
a control circuit configured to control an operation of the memory cell;
a row control circuit connected to the word line;
a column control circuit connected to the bit line;
a switch circuit connected to the row control circuit and the column control circuit; and
a read circuit connected to the switch circuit,
wherein the variable resistance element includes:
a first layer including a first compound including oxygen;
a second layer including a second compound including oxygen; and
a third layer between the first layer and the second layer, and
wherein at a time of a read operation of data from the memory cell,
the switch circuit is configured to connect the read circuit to the row control circuit in a first detection process in the read operation, and the read circuit is configured to detect a first signal which is output from the memory cell to the word line,
the switch circuit is configured to connect the read circuit to the column control circuit in a second detection process in the read operation, and the read circuit is configured to detect a second signal which is output from the memory cell to the bit line, and
the control circuit is configured to judge the data in the memory cell, based on the first signal and the second signal.

10. The device according to claim 9 , wherein the variable resistance element is configured to have one resistance state among a first resistance state, a second resistance state and a third resistance state in accordance with application of a voltage to the first layer and the second layer.

11. The device according to claim 9 , wherein the first compound is different from the second compound.

12. The device according to claim 9 , wherein the first compound includes nitrogen.

13. The device according to claim 9 , wherein a thickness of the first layer is different from a thickness of the second layer.

14. The device according to claim 9 , wherein each of the first compound and the second compound is at least one selected from the group consisting of titanium oxide, titanium oxynitride, tantalum oxide and tungsten oxide.

15. The device according to claim 9 , wherein a material of the third layer is at least one selected from the group consisting of amorphous silicon, amorphous silicon germanium, amorphous germanium, aluminum oxide, silicon oxide and hafnium oxide.

16. The device according to claim 9 , wherein the variable resistance element further includes:
a first electrode,
a second electrode, and
a stacked body disposed between the first electrode and the second electrode, the stacked body including the first layer, the second layer and the third layer.

Assignees

• Toshiba Memory Corp

Inventors

• Ota Kensuke
• Suzuki Masamichi
• Ichihara Reika

Classifications

• G11C2013/0057

  Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value · CPC title

• G11C2213/54

  Structure including a tunneling barrier layer, the memory effect implying the modification of tunnel barrier conductivity · CPC title

• G11C13/0007 Primary

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C2213/51

  Structure including a barrier layer preventing or limiting migration, diffusion of ions or charges or formation of electrolytes near an electrode · CPC title

• G11C2213/72

  Array wherein the access device being a diode · CPC title