Resistive random access memory and manufacturing and control methods thereof

Patent metadata

Field	Value
Publication number	US-2016148684-A1
Application number	US-201514950689-A
Country	US
Kind code	A1
Filing date	Nov 24, 2015
Priority date	Nov 26, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

A high-reliability resistive random access memory (RRAM). A memory cell of a memory cell array is controlled via a word line, a bit line and a source line. The control unit of the RRAM has a word line decoder, a bit line decoder, and a source line decoder and switch circuit. The word line decoder, the bit line decoder and the source line decoder respectively control the voltage applied to the word line, the voltage applied to the bit line, and the voltage applied to the source line. The switch circuit is switched between a first state and a second state to operate the bit line decoder to apply a voltage to the bit line to read the memory cell and to operate the source line decoder to apply a voltage to the source line to read the memory cell alternately.

First claim

What is claimed is:

1 . A resistive random access memory, comprising:
a plurality of memory cells provided within a memory cell array, each memory cell controlled via a word line, a bit line and a source line; and a control unit comprising:
a word line decoder, operative to set a voltage for the word line;
a bit line decoder, operative to set a voltage for the bit line;
a source line decoder, operative to set a voltage for the source line; and
a switch circuit, switched between a first state and a second state to operate the bit line decoder to apply a read voltage to the bit line to read the memory cell and to operate the source line decoder to apply a read voltage to the source line to read the memory cell alternately.

2 . The resistive random access memory as claimed in claim 1 , wherein:
every M times after the control unit operates the bit line decoder to apply the read voltage to the bit line to read the memory cell, the control unit switches the switch circuit and thereby the control unit changes to operate the source line decoder to apply the read voltage to the source line to read the memory cell; and M is a nonzero number.

3 . The resistive random access memory as claimed in claim 2 , wherein:
every N times after the control unit operates the source line decoder to apply the read voltage to the source line to read the memory cell, the control unit switches the switch circuit and thereby the control unit changes to operate the bit line decoder to apply the read voltage to the bit line to read the memory cell; and N is a nonzero number.

4 . The resistive random access memory as claimed in claim 1 , wherein:
the memory cell comprises a resistor and a transistor connected in series; and the transistor has a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the source line.

5 . The resistive random access memory as claimed in claim 1 , wherein:
the switch circuit is a flip-flop.

6 . A manufacturing method for a resistive random access memory, comprising:
manufacturing a switch circuit in a control unit of the resistive random access memory; and repeatedly reading a memory cell of the resistive random access memory for a reliability test, by which the switch circuit is switched between a first state and a second state and thereby a bit line decoder is operated to apply a read voltage to a bit line to read the memory cell and a source line decoder is operated to apply a read voltage to a source line to read the memory cell alternately, wherein the memory cell is provided within a memory cell array and controlled via a word line, the bit line and the source line.

7 . The manufacturing method as claimed in claim 6 , wherein:
every M times after the bit line decoder applies the read voltage to the bit line to read the memory cell, the switch circuit is switched to operate the source line decoder to apply the read voltage to the source line to read the memory cell; and M is a nonzero number.

8 . The manufacturing method as claimed in claim 7 , wherein:
every N times after the source line decoder applies the read voltage to the source line to read the memory cell, the switch circuit is switched to operate the bit line decoder to apply the read voltage to the bit line to read the memory cell; and N is a nonzero number.

9 . The manufacturing method as claimed in claim 6 , further comprising:
manufacturing a resistor and a transistor in the memory cell, wherein the resistor and the transistor are connected in series; and coupling a gate of the transistor to the word line, a drain of the transistor to the bit line and a source of the transistor to the source line.

10 . The manufacturing method as claimed in claim 6 , further comprising:
manufacturing a flip-flop to implement the switch circuit.

11 . A control method for a resistive random access memory, comprising:
providing a switch circuit in a control unit of the resistive random access memory; providing at least one read mode switching condition, wherein the switch circuit is switched between a first state and a second state according to the read mode switching condition; and reading a memory cell of the resistive random access memory, by applying a read voltage to a bit line coupled to the memory cell or to a source line coupled to the memory cell according to whether the read mode switching condition is satisfied, wherein the memory cell is provided within a memory cell array and controlled via a word line, the bit line and the source line.

12 . The control method as claimed in claim 11 , wherein the read mode switching condition includes:
switching the switch circuit to operate a source line decoder to apply the read voltage to the source line to read the memory cell after every M times of applying the read voltage to the bit line by a bit line decoder to read the memory cell; and M is a nonzero number.

13 . The control method as claimed in claim 12 , wherein the read mode switching condition further includes:
switching the switch circuit to operate the bit line decoder to apply the read voltage to the bit line to read the memory cell after every N times of applying the read voltage to the source line by the source line decoder to read the memory cell; and N is a nonzero number.

14 . The control method as claimed in claim 11 , further comprising:
providing a resistor and a transistor in the memory cell, wherein the resistor and the transistor are connected in series; and wherein a gate of the transistor is coupled to the word line, a drain of the transistor is coupled to the bit line and a source of the transistor is coupled to the source line.

15 . The control method as claimed in claim 11 , wherein the switch circuit is implemented by a flip-flop.

Assignees

• Winbond Electronics Corp

Inventors

• Lin Meng-Heng
• Wu Bo-Lun
• Wu Chien-Min

Classifications

• G11C2213/82

  Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C13/0033

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C13/0026 Primary

  Bit-line or column circuits · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title