Optimized scan interval

Patent metadata

Field	Value
Publication number	US-10446197-B2
Application number	US-201715692407-A
Country	US
Kind code	B2
Filing date	Aug 31, 2017
Priority date	Aug 31, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.

First claim

What is claimed is:

1. An apparatus comprising:
a memory device to receive read and write commands to read from and write to memory cells of an array of memory cells of the memory device;
one or more trackers to monitor parameters including a selected time interval, a number of read operations to read at least a portion of the memory device, and a number of at least one of write operations and erase operations to the at least the portion of the memory device; and
a calibration controller to trigger a read level calibration based on inputs from the one or more trackers and a determination of an occurrence of at least one event from a set of events including a monitored time equal to or exceeding the selected time interval, the number of the read operations equal to or exceeding a predetermined threshold for a number of read operations within the selected time interval, and the number of the at least one of write operations and erase operations equal to or exceeding a threshold for a number of at least one of write operations and erase operations within the selected time interval.

2. The apparatus of claim 1 , wherein the calibration controller includes firmware with stored instructions to determine the occurrence based on the inputs from the one or more trackers.

3. The apparatus of claim 1 , wherein the one or more trackers includes a read counter to count read commands sent to the memory device.

4. The apparatus of claim 1 , wherein the one or more trackers includes at least one of counter to count write and erase messages sent from the memory device in response to conducting at least one of an write and erase operation in the array.

5. The apparatus of claim 1 , wherein the one or more trackers includes a timer that is resettable to a reset value by the calibration controller to begin another wait interval for a read level calibration at the selected time interval from the reset value, and the calibration controller is operable to reset the one or more trackers to track read operations and track at least one of write operations and erase operations from the reset value of the timer.

6. The apparatus of claim 1 , wherein the triggered read level calibration includes a sampling of memory raw bit error rates at different read voltages to select a set of read voltages associated with a least raw bit error rate.

7. The apparatus of claim 1 , wherein the calibration controller is operable to track memory cell threshold voltage movement of the memory cells under stress conditions.

8. The apparatus of claim 1 , wherein the array of memory cells of the memory device is structured in a three-dimensional NAND configuration.

9. A system comprising:
a host processor;
a controller coupled to communicate with the host processor;
a set of memory devices coupled to the controller, the set of memory devices including a NAND memory device having an array of memory cells to which read and write commands are received from the controller to read from and write to memory cells of the NAND memory device;
a set of trackers to monitor time, to track read operations to the memory device, and to track write and/or erase operations communicated from the NAND memory device; and
a calibration controller to trigger read level calibration based on inputs from the set of trackers and a determination of an occurrence of at least one event from a set of events including the monitored time exceeding a selected time interval, a number of the read operations equal to or exceeding a predetermined threshold for a number of read operations within the selected time interval, and a number of the write and/or erase operations exceeding a threshold for a number of write and/or erase operations within the selected time interval.

10. The system of claim 9 , wherein the calibration controller includes firmware with stored instructions to determine the occurrence based on the inputs from the set of trackers.

11. The system of claim 9 , wherein the tracker to track read operations to the NAND memory device includes a read counter to count read commands sent from the controller to the NAND memory device, and the tracker to track write and/or erase operations communicated from the NAND memory device includes a write and/or erase counter to count write and/or erase messages sent by the NAND memory device in response to conducting an write and/or erase operations in the array.

12. The system of claim 9 , wherein the tracker to monitor time includes a timer that is resettable to a reset value by the calibration controller to begin another wait interval for a read level calibration at the selected time interval from the reset value, and the calibration controller is operable to reset the tracker to track read operations and the tracker to track write and/or erase operations to track from the reset value of the timer and within the selected time interval.

13. The system of claim 9 , wherein the system includes a flash translation layer that generates read and write operations to the NAND memory device via the controller to manage garbage collection of the array of memory cells of the NAND memory device.

14. A method comprising:
determining a number of read operations of a memory array of a memory structure and a number of at least one of write operations and erase operations of the memory array;
determining an occurrence of at least one event from a set of events including a monitored time equal to or exceeding a selected time interval, the determined number of read operations of the memory array equal to or exceeding a threshold for a number of read operations of the memory array within the selected time interval, and the determined number of at least one of write operations and erase operations of the memory array equal to or exceeding a threshold for a number of at least one of write operations and erase operations within the selected time interval; and
triggering a read level calibration of the memory array in response to the determination of the occurrence.

15. The method of claim 14 , wherein determining the number of read operations of the memory array includes counting read commands sent to read the memory array.

16. The method of claim 14 , wherein determining the number of at least one of write operations and erase operations of the memory array includes counting at least one of write messages and erase messages sent in response to conducting at least one of write operations and erase operations in the memory array.

17. The method of claim 14 , wherein the method includes conducting a read level calibration in response to the triggering, resetting a timer to begin another wait interval for a read level calibration at the selected time interval from the reset value of the timer, and resetting one or more trackers of a number of read operations and a number of at least one of write operations and erase operations of the memory array from the reset value of the timer and within the selected time interval.

18. The method of claim 17 , wherein resetting the one or more trackers includes resetting a read counter of a number of read operations and a counter of at least one of write operations and erase operations of the memory array.

19. The method of claim 14 , wherein the method includes conducting the triggered read level calibration by sampling memory raw bit error rates at different read voltages to select a set of read voltages with a least raw bit error rate.

20. The method of claim 14 , wherein the method includes tracking memory cell threshold voltage movement of

Assignees

• Micron Technology Inc

Inventors

• Muchherla Kishore Kumar
• Malshe Ashutosh
• Singidi Harish
• Alsasua Gianni Stephen
• Besinga Gary F
• Ratnam Sampath
• Feeley Peter Sean

Classifications

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G11C2216/22

  Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously · CPC title

• G11C8/10

  Decoders · CPC title

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title