Processors, methods, and systems for a configurable spatial accelerator with performance, correctness, and power reduction features

Patent metadata

Field	Value
Publication number	US-10445451-B2
Application number	US-201715640535-A
Country	US
Kind code	B2
Filing date	Jul 1, 2017
Priority date	Jul 1, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. At least one of the plurality of processing elements includes a plurality of control inputs.

First claim

What is claimed is:

1. A processor comprising:
a plurality of processing elements, wherein at least one of the processing elements is to perform a floating-point operation with selectable precision control; and
an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements.

2. The processor of claim 1 , wherein:
the at least one of the plurality of processing elements is configurable as a floating-point multiplier, at least an other of the plurality of processing elements is configurable as a floating-point adder, and the at least one and the at least an other of the plurality of processing elements are coupled together to perform a fused multiply-add.

Assignees

• Intel Corp

Inventors

• Fleming Kermin
• Glossop Kent D
• Steely Jr Simon C
• Tang Ping Tak Peter

Classifications

• H03K19/17758

  for speeding up configuration or reconfiguration · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F12/0862 Primary

  with prefetch · CPC title

• G06F12/0895

  of parts of caches, e.g. directory or tag array · CPC title

• G06F12/0888

  using selective caching, e.g. bypass · CPC title