Processors and methods for privileged configuration in a spatial array

Patent metadata

Field	Value
Publication number	US-10445098-B2
Application number	US-201715721809-A
Country	US
Kind code	B2
Filing date	Sep 30, 2017
Priority date	Sep 30, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

Methods and apparatuses relating to privileged configuration in spatial arrays are described. In one embodiment, a processor includes processing elements; an interconnect network between the processing elements; and a configuration controller coupled to a first subset and a second, different subset of the plurality of processing elements, the first subset having an output coupled to an input of the second, different subset, wherein the configuration controller is to configure the interconnect network between the first subset and the second, different subset of the plurality of processing elements to not allow communication on the interconnect network between the first subset and the second, different subset when a privilege bit is set to a first value and to allow communication on the interconnect network between the first subset and the second, different subset of the plurality of processing elements when the privilege bit is set to a second value.

First claim

What is claimed is:

1. A processor comprising:
a plurality of processing elements;
an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the interconnect network and the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements; and
a configuration controller coupled to a first subset and a second, different subset of the plurality of processing elements, the first subset of the plurality of processing elements having an output coupled to an input of the second, different subset of the plurality of processing elements according to configuration bits, wherein the configuration controller is to configure the interconnect network between the first subset and the second, different subset of the plurality of processing elements to not allow communication on the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when a privilege bit, separate from the configuration bits, is set, without modifying the configuration bits, to a first value and to allow communication on the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when the privilege bit is set, without modifying the configuration bits, to a second value.

2. The processor of claim 1 , wherein the interconnect network comprises a privilege state register at a boundary between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements to turn on and off a circuit at the boundary to not allow communication on the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when the privilege bit in the privilege state register is set by the configuration controller to the first value and to allow communication on the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when the privilege bit in the privilege state register is set by the configuration controller to the second value.

3. The processor of claim 1 , wherein a first context is to execute on the first subset of the plurality of processing elements and a second context is to concurrently execute on the second, different subset of the plurality of processing elements without allowing communication on the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when the privilege bit is set to the first value.

4. The processor of claim 1 , wherein the configuration controller is to not allow communication on a forward data path and a backward-flowing flow control path that is paired with the forward data path of the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when the privilege bit is set to the first value.

5. The processor of claim 1 , wherein the configuration controller is cause the interconnect network to pull all signals at a boundary between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements to zero when the privilege bit is set to the first value.

6. The processor of claim 1 , wherein the configuration controller is coupled to the first subset, the second, different subset, and a third, different subset of the plurality of processing elements, the first subset of the plurality of processing elements having the output coupled to the input of the second, different subset of the plurality of processing elements and the third, different subset of the plurality of processing elements having an output coupled to another input of the second, different subset of the plurality of processing elements, wherein the configuration controller is to configure the interconnect network between the first subset, the second, different subset, and the third, different subset of the plurality of processing elements to not allow communication on the interconnect network between the first subset, the second, different subset, and the third, different subset of the plurality of processing elements when the privilege bit is set to the first value and to allow communication on the interconnect network between the first subset, the second, different subset, and the third, different subset of the plurality of processing elements when the privilege bit is set to the second value.

7. The processor of claim 1 , wherein the configuration controller is to configure the first subset and the second, different subset of the plurality of processing elements according to configuration bits for a first context of the dataflow graph, and, for a requested context switch, configure the first subset of the plurality of processing elements according to configuration bits for a second context of the dataflow graph after pending operations of the first context are completed in the first subset and block second context dataflow into the input of the second, different subset of the plurality of processing elements from the output of the first subset of the plurality of processing elements until pending operations of the first context are completed in the second, different subset of the plurality of processing elements when the privilege bit is set to the second value.

8. The processor of claim 1 , wherein the configuration controller is to modify the privilege bit during runtime of the operation without modifying the configuration bits.

9. A method comprising:
performing an operation of a dataflow graph with an interconnect network and a plurality of processing elements of a processor when an incoming operand set arrives at the plurality of processing elements, wherein the processor comprises the plurality of processing elements and the interconnect network between the plurality of processing elements, and the dataflow graph comprising a plurality of nodes is overlaid into the plurality of processing elements of the processor and the interconnect network between the plurality of processing elements of the processor according to configuration bits with each node represented as a dataflow operator in the interconnect network and the plurality of processing elements; and
configuring, with a configuration controller of the processor, the interconnect network between a first subset and a second, different subset of the plurality of processing elements to not allow communication on the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when a privilege bit, separate from the configuration bits, is set, without modifying the configuration bits, to a first value and to allow communication on the interconnect network between the first subset of the plurality of processing elements and the second, different subset of the plurality of processing elements when the privilege bit is set, without modifying the configuration bits, to a second value.

10. The method of claim 9 , wherein the configuring comprises the configuration controller upda

Assignees

• Intel Corp

Inventors

• Fleming Kermin E
• Steely Simon C
• Glossop Kent D

Classifications

• G06F9/4403

  Processor initialisation · CPC title

• G06F1/14 Primary

  Time supervision arrangements, e.g. real time clock · CPC title

• G06F9/544

  Buffers; Shared memory; Pipes · CPC title

• G06F9/3017 Primary

  Runtime instruction translation, e.g. macros · CPC title

• G06F9/4843 Primary

  by program, e.g. task dispatcher, supervisor, operating system · CPC title