Magnetic Field Sensor With Feedback Loop For Test Signal Processing
US-2019079146-A1 · Mar 14, 2019 · US
US10444299B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10444299-B2 |
| Application number | US-201715700603-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 11, 2017 |
| Priority date | Sep 11, 2017 |
| Publication date | Oct 15, 2019 |
| Grant date | Oct 15, 2019 |
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A sensor circuit is provided with a chopper-stabilized amplifier circuit configured to receive a signal from at least one magnetic sensing element, a sigma-delta modulator (SDM) configured to receive a signal from the chopper-stabilized amplifier circuit, and a feedback circuit configured to reduce ripple in a signal generated by the chopper-stabilized amplifier circuit. The feedback circuit includes a demodulator to demodulate a signal from the SDM in a digital domain by inverting a bit stream of the signal from the SDM according to a frequency chopping rate, a digital integrator configured to integrate an output signal of the demodulator to form an integrated signal, and a digital-to-analog converter (DAC) configured to convert the integrated signal to an analog signal and provide the analog signal to the chopper-stabilized amplifier circuit.
Opening claim text (preview).
What is claimed is: 1. A sensor circuit comprising: a chopper-stabilized amplifier circuit configured to receive a signal from at least one magnetic sensing element; a sigma-delta modulator (SDM) configured to receive a signal from the chopper-stabilized amplifier circuit; a feedback circuit configured to reduce a ripple in a signal generated by the chopper-stabilized amplifier circuit, comprising: a demodulator to demodulate a signal from the SDM in a digital domain by inverting a bit stream of the signal from the SDM according to a frequency chopping rate; a digital integrator configured to integrate an output signal of the demodulator to form an integrated signal; a digital-to-analog converter (DAC) configured to convert the integrated signal to an analog signal and provide the analog signal to the chopper-stabilized amplifier circuit; and a first decimation filter coupled to an output of the SDM, wherein the feedback circuit is coupled to the output of the first decimation filter, wherein the first decimation filter uses a first decimation rate being twice the frequency chopping rate. 2. The sensor circuit of claim 1 , wherein the DAC is a current steering DAC. 3. The sensor circuit of claim 1 , further comprising a second decimation filter coupled to an output of the first decimation filter. 4. The sensor circuit of claim 3 , wherein the second decimation filter comprises at least one notch filter to reduce the ripple. 5. The sensor circuit of claim 4 , further comprising a third decimation filter coupled to an output of the demodulator and to an input of the digital integrator. 6. The sensor circuit of claim 5 , wherein the third decimation filter uses a third decimation rate selected to adjust the exponential decay of the ripple. 7. The sensor circuit of claim 6 , further comprising a gain circuit coupled to an output of the digital integrator and an input of the DAC. 8. The sensor circuit of claim 7 , wherein the gain circuit is selected to adjust the ripple attenuation. 9. The sensor circuit of claim 7 , further comprising: a digital comparator coupled to the output of the third decimation filter; and a gain boost control coupled to the chopper-stabilized amplifier circuit. 10. The sensor circuit of claim 9 , wherein the digital comparator is configured to compare a value with zero. 11. The sensor circuit of claim 10 , wherein the digital comparator is configured to compare an input of the digital integrator to zero. 12. The sensor circuit of claim 11 , wherein a gain of an amplifier of the chopper-stabilized amplifier circuit is increased by the gain boost control in response to the input of the digital integrator being zero. 13. The sensor circuit of claim 1 , wherein the chopper-stabilized amplifier circuit comprises: a first switch to receive signals from the at least one magnetic sensing element; a first amplifier configured to receives signals from the first switch; a second switch configured to receive signals from the first amplifier; a second amplifier configured to receive signals from the second switch; a third switch configured to receive signals from the second amplifier; and a third amplifier configured to receive signals from the third switch. 14. The sensor circuit of claim 1 , wherein the at least one magnetic sensing element comprises at least one of a Hall effect element, a magnetoresistance element, or a magnetotransistor. 15. The sensor circuit of claim 14 , wherein the at least one Hall effect element comprises one or more of a planar Hall element, a vertical Hall element or a Circular Vertical Hall (CVH) element. 16. The sensor circuit of claim 14 , wherein the at least one magnetoresistive element comprises one or more of a giant magnetoresistance (GMR) element, an anisotropic magnetoresistance element (AMR), a tunneling magnetoresistance (TMR) element, and a magnetic tunnel junction (MTJ). 17. A sensor circuit comprising: a first means comprising a chopper-stabilized amplifier configured to receive a signal from at least one magnetic sensing element and generate a signal; a sigma-delta modulator (SDM) configured to receive a signal from the first means; a feedback circuit configured to reduce a ripple in the signal generated by the first means, comprising: a demodulator configured to demodulate a signal from the SDM in a digital domain by inverting a bit stream of the signal from the SDM according to a frequency chopping rate; a digital integrator configured to integrate an output signal of the demodulator to form an integrated signal; a second means to convert the integrated signal to an analog signal and to provide the analog signal to the first means; and a first decimation filter coupled to an output of the SDM, wherein the feedback circuit is coupled to the output of the first decimation filter, wherein the first decimation filter uses a first decimation rate being twice the frequency chopping rate. 18. The sensor circuit of claim 17 , further comprising a second decimation filter coupled to an output of the first decimation filter. 19. The sensor circuit of claim 18 , wherein the second decimation filter comprises at least one notch filter to reduce the ripple. 20. The sensor circuit of claim 19 , further comprising a third decimation filter coupled to an output of the demodulator and to an input of the digital integrator. 21. The sensor circuit of claim 20 , wherein the third decimation falter uses a third decimation rate selected to adjust the exponential decay of the ripple. 22. The sensor circuit of claim 21 , further comprising a gain circuit coupled to an output of the digital integrator and an input of the second means, wherein the gain circuit is selected to adjust the ripple. 23. The sensor circuit of claim 22 , further comprising: a digital comparator coupled to the output of the third decimation filter; and a gain boost control coupled to the first means, wherein the digital comparator compares a value with zero. 24. The sensor circuit of claim 23 , wherein the digital comparator is configured to compare an input of the digital integrator to zero, wherein a gain of an amplifier of the chopper-stabilized amplifier circuit is increased by the gain boost control in response to the input of the digital integrator being zero.
using feed-back or modulation techniques · CPC title
Treating the measured signals, e.g. removing offset or noise · CPC title
Compensation of undesirable effects, e.g. quantisation noise, overflow (stability problems H03H17/0461) · CPC title
DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers {(switched capacitor amplifiers H03F3/005)} · CPC title
Notch filters · CPC title
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