Solid state lighting devices with dielectric insulation and methods of manufacturing

US10439102B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10439102-B2
Application numberUS-201815910460-A
CountryUS
Kind codeB2
Filing dateMar 2, 2018
Priority dateAug 9, 2010
Publication dateOct 8, 2019
Grant dateOct 8, 2019

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The solid state lighting device also includes an indentation extending from the second semiconductor material toward the active region and the first semiconductor material and an insulating material in the indentation of the solid state lighting structure.

First claim

Opening claim text (preview).

I claim: 1. A method for forming a solid state lighting device, comprising: providing a solid state lighting (SSL) structure on a substrate material, the SSL structure including a first semiconductor material and an active region over the first semiconductor material; forming an indentation in the SSL structure, thereby exposing sidewalls of the first semiconductor material and the active region; depositing an insulating material over the SSL structure, the insulating material covering exposed portions of the first semiconductor material and the active region in the indentation; and depositing a second semiconductor material on the SSL structure over the indentation and a surface of the active region, the second semiconductor material including (a) a first portion in contact with the active region and (b) a second portion in the indentation and separated from the first semiconductor material by the insulating material. 2. The method of claim 1 wherein the indentation is a V-shaped indentation. 3. The method of claim 1 wherein the sidewalls of the indentation converge toward one another as they extend toward the first semiconductor material. 4. The method of claim 1 , further comprising depositing a conductive material over the second semiconductor material. 5. The method of claim 1 wherein depositing the insulating material over the SSL structure includes depositing the insulating material over an upper surface of the active region, the method further comprising: prior to depositing the second semiconductor material, removing the insulative material over the upper surface of the active region, the insulating material in the indentation remaining. 6. The method of claim 5 , wherein depositing the insulating material includes depositing the insulating material prior to forming a conductive material over the second semiconductor material. 7. The method of claim 6 , further comprising depositing a conductive material over both the second semiconductor material and the insulating material in the indentation. 8. The method of claim 5 , wherein the insulating material remaining in the indentation generally fills the indentation. 9. The method of claim 1 , wherein depositing the insulating material includes depositing the insulating material in the indentation and generally conforming to the sidewalls of the indentation. 10. The method of claim 1 , wherein depositing the insulating material over the SSL structure includes at least partially filling the indentation with the insulating material.

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What does patent US10439102B2 cover?
Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The solid state lighting device also includes an indentat…
Who is the assignee on this patent?
Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification H01L33/025. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 08 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).