Semiconductor devices

Patent metadata

Field	Value
Publication number	US-10439033-B2
Application number	US-201615350425-A
Country	US
Kind code	B2
Filing date	Nov 14, 2016
Priority date	Jul 23, 2013
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

A semiconductor device can include a substrate with a first source/drain and a second source/drain in the substrate. A first ohmic contact pattern can be in an uppermost surface of the first source/drain, where the first ohmic contact pattern includes a first semiconductor alloyed with a first metal. A second ohmic contact pattern can be in an uppermost surface of the second source/drain, where the second ohmic contact pattern includes a second semiconductor that is different than the first semiconductor and is alloyed with a second metal that is different than the first metal.

First claim

What is claimed:

1. A semiconductor device comprising:
a substrate including a first region and a second region;
a first source/drain on the first region;
a first gate electrode at a side of the first source/drain;
a first sidewall protection pattern at an opposite side of the first source/drain;
a second source/drain on the second region;
a second gate electrode at a side of the second source/drain;
a second sidewall protection pattern at an opposite side of the second source/drain;
a first ohmic contact pattern in an uppermost surface of the first source/drain, wherein the first ohmic contact pattern includes a first semiconductor alloyed with a first metal;
a second ohmic contact pattern in an uppermost surface of the second source/drain, wherein the second ohmic contact pattern includes a second semiconductor that is different than the first semiconductor and is alloyed with a second metal that is different than the first metal; and
a sacrificial layer interposed between the first source/drain and the first sidewall protection pattern, the sacrificial layer including the first semiconductor,
wherein the first ohmic contact pattern directly contacts an uppermost surface of the sacrificial layer.

2. The semiconductor device of claim 1 , wherein the first ohmic contact pattern comprises a metal-Germanide, and-the second ohmic contact pattern comprises a metal-Silicide.

3. The semiconductor device of claim 1 , wherein the first ohmic contact pattern further comprises an alloy of the first metal and the second semiconductor.

4. The semiconductor device of claim 3 wherein the first ohmic contact pattern further comprises a first upper alloy of the second metal and the first semiconductor.

5. The semiconductor device of claim 4 wherein the first ohmic contact pattern further comprises a second upper alloy of the second metal and the second semiconductor.

6. The semiconductor device of claim 5 wherein the first upper alloy and the second upper alloy are more concentrated in an uppermost portion of the first ohmic contact pattern than in a lowermost portion of the first ohmic contact pattern closest to the first source/drain.

7. The semiconductor device of claim 1 wherein the first metal comprises one selected from a list consisting of Ti, Ni, Co, and/or Pt and the second metal comprises one selected from a list consisting of Ti, Ni, Co, and/or Pt.

8. The semiconductor device of claim 1 wherein:
the first region is a PMOS region;
the second region is an NMOS region.

9. The semiconductor device of claim 1 wherein a lowermost surface of the sacrificial layer is at a height higher than a lowermost surface of the first source/drain.

10. The semiconductor device of claim 9 wherein the sacrificial layer is undoped.

11. The semiconductor device of claim 9 wherein a lowermost surface of the first sidewall protection pattern is at a height higher than the lowermost surface of the first source/drain.

12. A semiconductor device comprising:
a substrate;
a first source/drain of a MOS device;
a gate electrode structure of the MOS device;
a sidewall protection pattern at a side of the first source/drain opposite the gate electrode structure;
a sacrificial layer comprising a first semiconductor, the sacrificial layer interposed between the first source/drain and the first sidewall protection pattern and contacting a side wall of the first source/drain; and
a first ohmic contact pattern on an uppermost surface of the first source/drain and including the first semiconductor alloyed with a first metal, wherein the first ohmic contact pattern extends from the uppermost surface of the first source/drain onto an uppermost surface of the sacrificial layer, wherein the first ohmic contact pattern directly contacts the uppermost surface of the sacrificial layer.

13. The semiconductor device of claim 12 wherein a composition of the sacrificial layer is different than a composition of the first source/drain.

14. The semiconductor device of claim 12 wherein the sacrificial layer comprises Germanium and the first source/drain comprises SiGe.

15. The semiconductor device of claim 12 wherein the sacrificial layer comprises an undoped epi-grown sacrificial layer.

16. The semiconductor device of claim 12 wherein the first ohmic contact pattern further comprises a lower alloy of the first semiconductor and the first metal and an upper alloy on the lower alloy, the upper alloy comprising an alloy of a second semiconductor and a second metal that is different than the first metal, wherein the second semiconductor is different than the first semiconductor.

17. The semiconductor device of claim 12 wherein the MOS device comprises a PMOS device in a PMOS region of the semiconductor device, the semiconductor device further comprising:
an NMOS gate electrode structure of an NMOS device in an NMOS region of the semiconductor device;
a second source/drain of the NMOS device; and
an uppermost surface of the second source/drain includes an unsilicided portion closest to the NMOS gate electrode structure.

18. The semiconductor device of claim 17 wherein the unsilicided portion is located between a side wall of the NMOS gate electrode structure and an opposing side wall of a silicided portion of the uppermost surface of the second source/drain.

19. The semiconductor device of claim 12 wherein a lowermost surface of the sacrificial layer is at a height higher than a lowermost surface of the first source/drain.

20. The semiconductor device of claim 19 wherein a lowermost surface of the sidewall protection pattern is at a height higher than the lowermost surface of the first source/drain.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Xiong Junjie
• Cha Dongho
• Kang Myung Jin
• Do Kihoon

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H01L21/823814

  Electricity · mapped topic

• H01L27/092

  Electricity · mapped topic