Reliable passivation for integrated circuits

Patent metadata

Field	Value
Publication number	US-10438909-B2
Application number	US-201715429198-A
Country	US
Kind code	B2
Filing date	Feb 10, 2017
Priority date	Feb 12, 2016
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is provided. A pad dielectric layer is formed over the BEOL dielectric layer. The pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer. A pad interconnect is formed on the pad dielectric layer and the pad interconnect is coupled to one of the interconnect in the BEOL dielectric by a pad via contact in the pad via opening. The pad interconnect comprises a pad interconnect pattern which is devoid of 90° angles and any angled structures contained in the pad interconnect pattern less than 90°. A passivation layer is formed on the substrate. The passivation layer lines the pad interconnect and covers an exposed surface of the pad dielectric layer.

First claim

What is claimed is:

1. A method of forming a device, comprising:
providing a substrate prepared with circuit components and a back-end-of-line (BEOL) dielectric layer with interconnects;
forming a pad dielectric layer over the BEOL dielectric layer, wherein the pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer;
depositing a pad conductive layer on a surface of the substrate, wherein the pad conductive layer fills the pad via opening and covers the pad dielectric layer;
depositing a resist layer on the pad conductive layer;
exposing the resist layer with a pad level reticle containing a pad interconnect pattern layout which is devoid of 90° angles due to corner rounding provided in the pad interconnect pattern layout by optical proximity correction;
developing the resist layer to transfer the pad interconnect pattern layout on the pad level reticle to the resist layer to form a patterned resist layer;
etching the pad conductive layer to remove portions unprotected by the patterned resist layer to form a plurality of pad interconnects separated by spaces, wherein the pad interconnects have a pad interconnect pattern which is devoid of 90° angles; and
forming a composite passivation liner on the pad dielectric layer and the pad interconnects, wherein the composite passivation liner includes a first dielectric liner conformally lining the pad dielectric layer and the pad interconnects, the composite passivation liner includes a second dielectric liner disposed on the first dielectric liner, the first dielectric liner is comprised of silicon oxide and has a thickness of about 4,000 Å to about 6,000 Å, the second dielectric liner is comprised of silicon nitride and has a thickness of about 4,000 Å to 6,000 Å, and the second passivation dielectric liner conformally lines the first dielectric liner.

2. The method of claim 1 wherein etching the pad conductive layer comprises:
over-etching the pad conductive layer to ensure complete removal of portions of the pad conductive layer unprotected by the patterned resist layer.

3. The method of claim 1 wherein the pad interconnects having the pad interconnect pattern which is devoid of 90° angles functions to increase the integrity of the composite passivation liner in thermal cycle testing ranging from about −65° C. to about 150° C.

4. The method of claim 1 wherein the pad interconnect pattern includes angles of about 45°.

5. The method of claim 1 wherein the pad conductive layer has a thickness greater than about 20,000 Å.

6. The method of claim 1 wherein the composite passivation liner conformally lines the pad dielectric layer and the pad interconnects without filling the spaces between the pad interconnects.

7. The method of claim 1 wherein the second dielectric liner is disposed completely and directly on the first dielectric liner.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Lee Fook Hong
• Tan Juan Boon
• KHOR Ee Jan

Classifications

• H10W72/5525

  comprising copper [Cu] · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W72/01953

  by etching · CPC title

• H10W72/01951

  Changing the shapes of bond pads · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title