Semiconductor chip package having heat dissipating structure

Patent metadata

Field	Value
Publication number	US-10438873-B2
Application number	US-201715617126-A
Country	US
Kind code	B2
Filing date	Jun 8, 2017
Priority date	Aug 4, 2016
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

Disclosed herein is a semiconductor chip package having a heat dissipating structure. The semiconductor chip package including: a semiconductor chip configured such that a plurality of terminals protrudes from the upper surface thereof; lead frames connected to the terminals located on the upper surface of the semiconductor chip; and a package body configured to protect the semiconductor chip and the lead frames and to form the outside shape of the semiconductor chip package, and formed by molding. The lower surfaces of the lead frames are exposed to the outside. The lower surface of the package body is partially cut out such that the bottom surface of the semiconductor chip is exposed to the outside.

First claim

What is claimed is:

1. A semiconductor chip package comprising:
a semiconductor chip configured such that terminals made of a solder material are formed on a first surface thereof and are arranged in two rows along a longitudinal direction, and the terminals are not formed on a second surface thereof, which is a bottom surface;
lead frames indirectly connected to the terminals of the semiconductor chip;
clip members each disposed between the semiconductor chip and one of the lead frames, and configured to enable the terminals to be indirectly connected to the lead frames; and
a package body configured to protect the semiconductor chip, the lead frames, and the clip members and to form an outside shape of the semiconductor chip package, and formed by molding;
wherein the package body is partially cut out such that the second surface of the semiconductor chip is exposed to an outside, the second surface being disposed at a step down by a predetermined depth from an exterior surface of the package body;
wherein the terminals are connected to the lead frames in a state in which the terminals of the semiconductor chip have been oriented toward an inside of the package body;
wherein side surfaces of the lead frames in a same orientation with longitudinal side surfaces of the package body are exposed to the outside;
wherein each of the lead frames includes a first lower surface exposed to the outside, and a second lower surface formed at a step down by a predetermined depth from the first lower surface such that the second lower surface is disposed inside the package body;
wherein each of the clip members is connected to a portion of each of the lead frames including the second lower surface;
wherein the first surface is a lower surface of the semiconductor chip, the second surface is an upper surface of the semiconductor chip, and the bottom surface of the semiconductor chip is exposed via an upper surface of the package body; and
wherein the lead frames are formed in a non-bent shape and disposed at locations lower than the terminals of the semiconductor chip, and the clip members connected to the lead frames are bent upward to locations of the terminals and connected to the terminals.

2. The semiconductor chip package of claim 1 , wherein the terminals protrude from the first surface of the semiconductor chip.

3. A semiconductor chip package comprising:
a semiconductor chip configured such that terminals made of a solder material are formed on a first surface thereof and are arranged in two rows along a longitudinal direction, and the terminals are not formed on a second surface thereof, which is a bottom surface;
lead frames indirectly connected to the terminals of the semiconductor chip;
clip members each disposed between the semiconductor chip and one of the lead frames, and configured to enable the terminals to be indirectly connected to the lead frames; and
a package body configured to protect the semiconductor chip, the lead frames, and the clip members and to form an outside shape of the semiconductor chip package, and formed by molding;
wherein the package body is partially cut out such that the second surface of the semiconductor chip is exposed to an outside, the second surface being disposed at a step down by a predetermined depth from an exterior surface of the package body;
wherein the terminals are connected to the lead frames in a state in which the terminals of the semiconductor chip have been oriented toward an inside of the package body;
wherein side surfaces of the lead frames in a same orientation with longitudinal side surfaces of the package body are exposed to the outside;
wherein each of the lead frames includes a first lower surface exposed to the outside, and a second lower surface formed at a step down by a predetermined depth from the first lower surface such that the second lower surface is disposed inside the package body;
wherein each of the clip members is connected to a portion of each of the lead frames including the second lower surface;
wherein the first surface is an upper surface of the semiconductor chip, the second surface is a lower surface of the semiconductor chip, and the bottom surface of the semiconductor chip is exposed via a lower surface of the package body; and
wherein the lead frames are formed in a non-bent shape and disposed at locations lower than the terminals of the semiconductor chip, and the clip members connected to the lead frames are bent upward to locations of the terminals and connected to the terminals.

Assignees

• Jmj Korea Co Ltd

Inventors

• Choi Yunhwa
• Cho Jeonghun

Classifications

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10W70/468

  Circuit boards · CPC title