Semiconductor structures having low resistance paths throughout a wafer

Patent metadata

Field	Value
Publication number	US-10438803-B2
Application number	US-201514832024-A
Country	US
Kind code	B2
Filing date	Aug 21, 2015
Priority date	May 19, 2014
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

First claim

What is claimed is:

1. A method, comprising:
forming a silicide layer directly on an underlying substrate of a wafer;
forming an interlevel dielectric material directly in contact with the silicide layer;
forming one or more metal wiring and interconnects in the interlevel dielectric material such that an entire bottom surface of said one or more metal wiring and interconnects is covered by said interlevel dielectric material, wherein the one or more metal wiring and interconnects are separated from the silicide layer by a portion of the interlevel dielectric material;
forming a seed layer and barrier layer on an upper surface of the interlevel dielectric material, contacting directly an upper surface of the one or more underlying metal wiring and interconnects;
forming a metal wiring in direct contact with the seed layer;
forming a plurality of devices in direct contact with the silicide layer, the silicide layer extending between the devices such that sides of the devices are in direct contact with the silicide layer and the interlevel dielectric material and with a center of the devices directly below the one or more metal wiring and interconnects and the metal wiring such that the devices are electrically isolated from the one or more metal wiring and interconnects and metal wiring by the interlevel dielectric material; and
removing exposed portions of the seed layer and barrier layer by a wet etch process.

2. The method of claim 1 , wherein the barrier layer is formed in direct contact with conductive material of the metal wiring and interconnects.

3. The method of claim 2 , wherein the seed layer has a thickness of about 500 Å to about 1 micron.

4. The method of claim 1 , wherein the metal wiring is formed by depositing and patterning a resist on the interlevel dielectric material and over the seed layer and barrier layer, patterning the resist to form openings and depositing metal material in the openings.

5. The method of claim 4 , wherein the depositing metal material in the openings is an electroplating.

6. The method of claim 5 , wherein after formation of the metal wiring, the resist is removed.

7. The method of claim 1 , wherein the plurality of devices are active or passive devices formed on the substrate.

8. The method of claim 7 , wherein the active or passive devices formed on the substrate are each spaced apart from and directly below a corresponding one of the one or more metal wiring and interconnects.

9. The method of claim 1 , wherein the silicide layer is directly on and contacting the substrate, the interlevel dielectric material is directly on and contacting the silicide layer, and the one or more metal wiring and interconnects are entirely electrically isolated from the silicide layer by the interlevel dielectric material.

10. The method of claim 1 , wherein the silicide layer is a conductive path for electroplating.

11. The method of claim 1 , wherein the removing the exposed portions of the seed layer and barrier layer comprises removing portions of the seed layer and barrier layer which are left exposed by the metal wiring.

12. The method of claim 11 , wherein a thickness of the seed layer and barrier layer is configured for improving a critical dimension loss.

13. The method of claim 12 , wherein the dimension loss is a lateral critical dimension loss.

14. The method of claim 13 , wherein the wet etch process is a short wet etch process.

15. The method of claim 14 , wherein the metal wiring is a BEOL metal wiring.

16. The method of claim 15 , wherein the BEOL metal wiring allows for a reduction in the thickness of the seed layer and barrier layer.

17. The method of claim 16 , wherein the short wet etch process does not remove the BEOL metal wiring due to its overall thickness compared to the thickness of the seed layer and barrier layer.

18. The method of claim 17 , further comprising forming the metal wiring in contact with the seed layer as an embedded BEOL wiring structure inside a chip interior for chip power distribution and grounding.

19. The method of claim 18 , wherein the BEOL wiring structure is configured to reduce a thickness of the seed layer.

20. The method of claim 19 , wherein the BEOL wiring structure is configured to provide a lower Rs path for electroplating processes.

Assignees

• IBM

Inventors

• Gambino Jeffrey P
• Hartswick Thomas J
• He Zhong-Xiang
• Stamper Anthony K
• White Eric J

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P14/418

  the conductive layers comprising transition metals · CPC title

• H10P14/414

  of metal-silicide materials · CPC title

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10P14/46

  using a liquid · CPC title