Memory device and information processing system

Patent metadata

Field	Value
Publication number	US-10438665-B2
Application number	US-201715695563-A
Country	US
Kind code	B2
Filing date	Sep 5, 2017
Priority date	Mar 21, 2017
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

According to one embodiment, a memory device is connected to one or more information processing devices. The memory device includes a shared memory and a memory controller. The memory controller is configured to analyze an access to the shared memory by the one or more information processing devices and decide on an access method for accessing the shared memory by the one or more information processing devices. The memory controller is configured to give an instruction indicating the decided access method to the one or more information processing devices.

First claim

What is claimed is:

1. A memory device connected to one or more information processing devices, each of the one or more information processing devices including an individual memory, the memory device comprising:
a shared memory that includes a first shared memory and a second shared memory having a faster response speed than the first shared memory;
an access controller configured to control writing of data and reading of data on the shared memory in response to an access request for accessing the shared memory from the one or more information processing devices; and
a memory controller configured to:
analyze an access to the shared memory by the one or more information processing devices and decide on an access method for accessing the shared memory by the one or more information processing devices, the access method being to be performed as a first access process of performing writing or reading of data transferred from the shared memory to the individual memory or a second access process of directly performing writing or reading of data stored in the shared memory;

set the decided access method in the access controller; and
give an instruction indicating the decided access method to the one or more information processing devices, wherein

the access controller performs writing of data or reading of data on the shared memory in accordance with the set access method,
each of the one or more information processing devices causes the access controller to transfer data from the shared memory to the individual memory and perform writing or reading of the data transferred to the individual memory when an instruction indicating the first access process is given,
each of the one or more information processing devices transmits a request for writing or reading the data stored in the shared memory to the access controller when an instruction indicating the second access process is given,
the memory controller further decides on a usage capacity in the individual memory when the access method is decided to be the first access process,
the memory controller further gives an instruction indicating the usage capacity to the one or more information processing devices, and
the memory controller further decides whether the second access process is to be performed as a low-speed process or a high-speed process when the access method is decided to be the second access process, wherein
when the low-speed process is set as the access method, the access controller directly performs writing or reading of the data stored in the first shared memory in accordance with an access request according to the second access process transmitted from each of the one or more information processing devices, and
when the high-speed process is set as the access method, the access controller directly performs writing or reading of data that is transferred from the first shared memory to the second shared memory, in accordance with an access request according to the second access process, the access request being transmitted from each of the one or more information processing devices.

2. The memory device according to claim 1 , wherein
each of the one or more information processing devices stores the data transferred from the shared memory in the corresponding individual memory within a range of the usage capacity indicated in the instruction.

3. The memory device according to claim 1 , wherein
the memory controller further decides on a saving method for saving data from the individual memory to the shared memory when the access method is decided to be the first access process,
the memory controller further gives an instruction indicating the saving method to the one or more information processing devices, and
each of the one or more information processing devices saves the data transferred from the shared memory from the corresponding individual memory to the shared memory in accordance with the saving method indicated in the instruction.

4. The memory device according to claim 1 , wherein
the memory controller gives an instruction indicating a degree of parallelism indicating the number of processes to be executed in parallel to the information processing device that transmits an access request according to the second access process,
the memory controller further detects a sub region that is likely to be accessed in the first shared memory when deciding that the second access process is performed as the high-speed process,
the access controller transfers data of the sub region in the first shared memory to the second shared memory in advance, and directly performs writing or reading of the data transferred to the second shared memory in advance in accordance with an access request according to the second access process for the sub region, the access request being transmitted from each of the one or more information processing devices,
the access controller directly writing or reading on the first shared memory in accordance with an access request according to the second access process for a region different from the sub region, the access request being transmitted from each of the one or more information processing devices, and
the memory controller gives an instruction indicating a first degree of parallelism to an information processing device that performs writing or reading of data on the second shared memory, and gives an instruction indicating a second degree of parallelism higher than the first degree of parallelism to an information processing device that performs writing or reading of data on the first shared memory.

5. The memory device according to claim 1 , wherein
the memory controller gives an instruction indicating a degree of parallelism indicating the number of processes to be executed in parallel to the information processing device that transmits an access request according to the second access process, and
the memory controller decides on the degree of parallelism in accordance with an access latency of a region in which data is written through the second access process.

6. A memory device connected to one or more information processing devices, each of the one or more information processing devices including an individual memory, the memory device comprising:
a shared memory that is divided into a plurality of regions;
an access controller configured to control writing of data and reading of data on the shared memory in response to an access request for accessing the shared memory from the one or more information processing devices; and
a memory controller configured to:
analyze an access to each of the plurality of regions by the one or more information processing devices and decides on an access method for accessing each of the plurality of regions by the one or more information processing devices, the access method being to be performed as a first access process of performing writing or reading of data transferred from each of the plurality of regions to the individual memory or a second access process of directly performing writing or reading of data stored in each of the plurality of regions;
set the decided access method in the access controller; and
give an instruction indicating the decided access method to the one or more information processing devices for each of the plurality of regions, wherein

the access controller performs writing of data or reading of data on a corresponding region in accordance with the access method set for each of the plurality of regions,
each of the one or more information processing devices causes the access controller to transfer data from the corresponding region to the individual memory and performs writing or reading of the data transferred to the individual memory when an instruction indicating the first access process is given,
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Assignees

• Toshiba Memory Corp

Inventors

• Shirota Yusuke
• Kanai Tatsunori
• Shirai Satoshi

Classifications

• G06F13/1663

  Access to shared memory · CPC title

• G11C7/1048

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C16/107 Primary

  Programming all cells in an array, sector or block to the same state prior to flash erasing · CPC title

• G11C5/148 Primary

  Details of power up or power down circuits, standby circuits or recovery circuits · CPC title

• G06F12/0646

  Configuration or reconfiguration · CPC title