Stochastic parallel microprocessor

Patent metadata

Field	Value
Publication number	US-10437561-B2
Application number	US-201615740983-A
Country	US
Kind code	B2
Filing date	Jun 17, 2016
Priority date	Jun 29, 2015
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

The invention relates to a stochastic-type microprocessor.
In some embodiments, the microprocessor comprises an elementary stochastic computation module able to receive, as input, two random and independent binary input signals each representing a binary coding of two respective given input probability values, and able to generate, as output, a random binary output signal.
The elementary module comprises:
a programmable logic unit, able to combine two input signals to generate an output signal; an addressable memory, able to store an output probability value coded by an output signal generated by the logic unit; a first stochastic clock, able to produce a first clock signal; a second stochastic clock, able to produce a second clock signal.

First claim

The invention claimed is:

1. A microprocessor comprising at least one elementary stochastic computation module configured to receive, as input, two random and independent binary input signals each representing a binary coding of two respective given input probability values, and to generate, as output, at least one random binary output signal from the two input signals, said at least one elementary stochastic computation module comprising:
at least one programmable logic unit, configured to combine the two input signals generate the output signal according to at least one determined logic function, such that the output signal represents a binary coding of an output probability value as a function of the given input probability values;
at least one addressable memory, configured to store said output probability value coded by the output signal generated by the at least one programmable logic unit;
at least one first stochastic clock, configured to produce a first random impulse clock signal to control a writing speed, in the at least one addressable memory, of the output probability value coded by the output signal generated by the at least one programmable logic unit; and
at least one second stochastic clock, configured to produce a second random impulse clock signal to control a reading speed of the at least one addressable memory, so as to provide a current evaluation, over a given time window, of the output probability value stored in the at least one addressable memory.

2. The microprocessor according to claim 1 , wherein the at least one elementary stochastic computation module is further configured to receive, as input, the two random and independent binary input signals, each of the two random and independent binary input signals comprising a stochastic impulse binary coding or a telegraphic temporal binary coding, respectively, of the two given input probability values, and to generate, as output, the random binary output signal, of the telegraphic or impulse type, and wherein the at least one programmable logic unit is further configured to combine the two input signals to generate the output signal according to the determined logic function, such that the output signal represents a stochastic impulse binary coding or a telegraphic temporal binary coding of the output probability value as a function of the given input probability values.

3. The microprocessor according to claim 1 , wherein the at least one programmable logic unit is configured to combine the two input signals to generate the output signal according to one or a plurality of product, sum or division functions, such that the output probability value coded by the output signal respectively corresponds to the product, the sum or the division, of the input probability values respectively coded by the two input signals.

4. The microprocessor according claim 1 , the microprocessor comprising a plurality of elementary stochastic computation modules according to claim 1 , the microprocessor further configured to generate, in parallel, at least two output signals via at least two elementary stochastic computation modules determined from among said elementary stochastic computation modules, to implement, in parallel, at least two corresponding stochastic computations.

5. The microprocessor according to claim 4 , wherein the at least two elementary stochastic computation modules are interconnected and configured to exchange signals between the at least two elementary stochastic computation modules.

6. The microprocessor according to claim 5 , wherein the at least one addressable memory of at least one of the two interconnected elementary stochastic computation modules is configured to store interconnection instructions relative to the interconnection and exchange of the input and output signals between the two interconnected elementary stochastic computation modules.

7. The microprocessor according to claim 4 , the microprocessor comprising at least two remote elementary stochastic computation modules and one or a plurality of addressable switch boxes configured to exchange input and output signals between the two remote elementary stochastic computation modules.

8. The microprocessor according to claim 1 , the microprocessor comprising one or a plurality of random signal generators each configured to generate a random binary signal generating a binary coding of a probability value associated with a binary number, and the at least one elementary stochastic computation module is further configured to receive, as input, two random and independent binary input signals generated by the one or plurality of random signal generators.

9. A computer system comprising at least one central memory configured to store instructions and at least one central processing unit configured to execute instructions stored in the at least one central memory, the central processing unit comprising at least one microprocessor according to claim 1 .

Assignees

• Centre Nat Rech Scient
• College France

Inventors

• Droulez Jacques
• Bessiere Pierre

Classifications

• G06F7/584

  using finite field arithmetic, e.g. using a linear feedback shift register · CPC title

• G06F7/70 Primary

  using stochastic pulse trains, i.e. randomly occurring pulses the average pulse rates of which represent numbers {(conversion of analogue signals into stochastic pulse trains and vice versa H03M1/04)} · CPC title

• G06F2207/582

  Parallel finite field implementation, i.e. at least partially parallel implementation of finite field arithmetic, generating several new bits or trits per step, e.g. using a GF multiplier · CPC title