Polysynchronous stochastic circuits

Patent metadata

Field	Value
Publication number	US-10520975-B2
Application number	US-201715448997-A
Country	US
Kind code	B2
Filing date	Mar 3, 2017
Priority date	Mar 3, 2016
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

In some examples, a device includes an integrated circuit and two or more computational units configured to process respective stochastic bit streams in accordance with respective input clocks. Each of the stochastic bit streams comprises sequential sets of data bits, each of the sets of data bits representing a numerical value based on a probability that any bit in the respective set of data bits is one. The respective input clocks for each of the two or more computational units are unsynchronized.

First claim

The invention claimed is:

1. A device comprising:
an integrated circuit including:
a first computational unit configured to receive, as inputs, at least two input stochastic bit streams driven by respective input clocks that are unsynchronized;
a second computational unit configured to produce one of the at least two input stochastic bit streams in accordance with one of the respective input clocks;
a third computational unit configured to produce another of the at least two input stochastic bit streams in accordance with another of the respective input clocks;
a central clock configured to generate a central clock signal; and
a clock distribution circuit configured to distribute the central clock signal to the second computational unit and the third computational unit as the unsynchronized respective input clocks without having timing elements that substantially synchronize arrival of the central clock signal to the second computational unit and the third computational unit,

wherein the at least two input stochastic bit streams received by the first computational unit are misaligned in time in accordance with the unsynchronized respective input clocks of the second computational unit and the third computational unit,
wherein the first computational unit is configured to process the misaligned input stochastic bit streams to compute a result and produce an output stochastic bit stream representative of the result, and
wherein each of the stochastic bit streams comprises sequential sets of data bits, each of the sets of data bits representing a numerical value based on a probability that any bit in the respective set of data bits is one.

2. The device of claim 1 , wherein the first computational unit is configured to tolerate a clock misalignment of at least ten percent, the clock misalignment representing a difference between arrival times for the respective input clocks at the second and third computational units.

3. The device of claim 2 , wherein the first computational unit is configured to tolerate a clock misalignment of at least fifty percent.

4. The device of claim 2 , wherein the first computational unit is configured to tolerate a clock misalignment of at least ninety percent.

5. The device of claim 1 ,
wherein each of the at least two input stochastic bit streams encodes image data, and
wherein the first computational unit is configured to perform image processing operations on the image data.

6. The device of claim 5 ,
wherein the device comprises an image processing device,
wherein the first, second, and third computational units include a first pixel processing unit of an array of pixel processing units,
wherein the at least two input stochastic bit streams include one or more input pixel values,
wherein each pixel processing unit of the array of pixel processing units is configured to convert an input pixel value into an output pixel value,
wherein each pixel processing unit of the array of pixel processing units includes a local clock configured to generate a respective input clock of the respective pixel processing unit, and
wherein the central clock comprises the respective local clock of the first pixel processing unit.

7. The device of claim 1 ,
wherein the first computational unit comprises a first logic gate configured to receive the at least two input stochastic bit streams, and
wherein the second and third computational units comprise a plurality of logic gates that are driven by the respective input clocks.

8. The device of claim 1 , wherein the first computational unit is configured to tolerate a word length skew of at least one bit position in the at least two input stochastic bit streams, the word length skew representing a difference between arrival times for a first bit of the at least two input stochastic bit streams.

9. The device of claim 1 ,
wherein the central clock is a first central clock and the central clock signal is a first central clock signal,
wherein the at least two input stochastic bit streams are a first set of input stochastic bit streams,
wherein the respective input clocks are a first set of respective input clocks,
wherein the integrated circuit further comprises:
a fourth computational unit configured to receive, as inputs, a second set of input stochastic bit streams driven by a second set of respective input clocks that are unsynchronized;
a fifth computational unit configured to produce one of the second set of input stochastic bit streams in accordance with one of the second set of respective input clocks;
a sixth computational unit configured to produce another of the second set of input stochastic bit streams in accordance with another of the second set of respective input clocks;
a second central clock configured to generate a second clock signal; and
a second clock distribution circuit configured to distribute the second central clock signal to the second computational unit and the third computational unit as the second set of unsynchronized respective input clocks without having timing elements that substantially synchronize arrival of the second central clock signal to the fifth and sixth computational units,

wherein each of the first and second clock signals is locally generated within the integrated circuit proximate respective computational units.

10. The device of claim 9 ,
wherein each of the first and second central clock signals has a respective period; and
wherein the integrated circuit is configured to tolerate a clock deviation of at least ten percent, the clock deviation representing a percent increase from a smaller one of the periods to a larger one of the periods for the first and second central clock signals.

11. The device of claim 10 , wherein the integrated circuit is configured to tolerate clock deviation of at least ninety percent.

12. The device of claim 9 ,
wherein each of the first and second sets of input stochastic bit streams encodes image data, and
wherein the first and sixth computational units are configured to perform image processing operations on the image data.

13. The device of claim 12 ,
wherein the device comprises an image processing device,
wherein the first, second, and third computational units include a first pixel processing unit of an array of pixel processing units,
wherein the fourth, fifth, and sixth computational units include a second pixel processing unit of the array of pixel processing units,
wherein the first and second sets of input stochastic bit streams include one or more input pixel values,
wherein each pixel processing unit of the array of pixel processing units is configured to convert an input pixel value into an output pixel value,
wherein each pixel processing unit of the array of pixel processing units includes a local clock configured to generate a respective input clock of the respective pixel processing unit,
wherein the first central clock comprises the respective local clock of the first pixel processing unit, and
wherein the second central clock comprises the respective local clock of the second pixel processing unit.

14. The device of claim 9 ,
wherein the first computational unit comprises a first logic gate that receives the first set of input stochastic bit streams,
wherein the sixth computational unit comprises a second logic gate that receives the second set of input stochastic bit streams,
wherein the second and third computational units comprise a first set of logic gates that are driven by the first set of respective input clocks, and
wherein the fourth and fifth computational units comprise a second set of logic gates that are driv

Assignees

• Univ Minnesota

Inventors

• Lilja David J
• Najafi Mohammadhassan
• Riedel Marcus
• Bazargan Kiarash

Classifications

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F7/70

  using stochastic pulse trains, i.e. randomly occurring pulses the average pulse rates of which represent numbers {(conversion of analogue signals into stochastic pulse trains and vice versa H03M1/04)} · CPC title

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06T1/00

  General purpose image data processing · CPC title