Pixel compression mechanism

Patent metadata

Field	Value
Publication number	US-10430990-B2
Application number	US-201715710828-A
Country	US
Kind code	B2
Filing date	Sep 20, 2017
Priority date	Sep 20, 2017
Publication date	Oct 1, 2019
Grant date	Oct 1, 2019

Abstract

An apparatus to facilitate pixel compression is disclosed. The apparatus includes a rasterizer module to convert an image to a plurality of pixels, an interface coupled to the rasterizer module, a depth check module coupled to the interface and compression logic to perform a compression encoding on the plurality of pixels, including dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks, determining coverage information for pixels in each of the plurality of pixel blocks, encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded block.

First claim

What is claimed is:

1. An apparatus to facilitate pixel compression comprising:
one or more processors to:
convert an image to a plurality of pixels;
encode the plurality of pixels, including:
dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks;
determining coverage information indicating a pixel span for each of the plurality of pixel blocks; and
encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded pixel block;
transmit the mega encoded pixel block for depth checking via an interface based on a multi-sample anti-aliasing case being implemented; and
transmit the coverage information via the interface.

2. The apparatus of claim 1 , wherein the one or more processors generate a first encoded control indicator and a mask including the coverage information of each pixel in a pixel block upon a determination that the pixel block has a first coverage type.

3. The apparatus of claim 2 , wherein the one or more processors generates only a second encoded control packet upon a determination that the pixel block has a second coverage type, and generates only a third encoded control packet upon a determination that the pixel block has a third coverage type.

4. The apparatus of claim 3 , wherein the one or more processors transmit the encoded mega pixel block to a depth check module as an encoded control packet including one or more encoded control indicators and a data packet including one or more masks including the coverage information for each of the plurality of pixel blocks in the mega pixel block.

5. The apparatus of claim 4 , wherein the interface comprises:
a first bus; and
a second bus.

6. The apparatus of claim 5 , wherein the encoded control packet is transmitted via the first bus and the data packet is transmitted via the second bus.

7. The apparatus of claim 4 , wherein the one or more processors decode the plurality of pixels received at the depth check module.

8. The apparatus of claim 7 , wherein the decoding comprises storing the one or more encoded control indicators and the data packet of the encoded mega pixel block.

9. The apparatus of claim 7 , wherein the decoding further comprises comparing each of the encoded pixel blocks to the stored encoded mega pixel block to determine coverage information for pixels in each of the encoded pixel blocks.

10. The apparatus of claim 9 , wherein the one or more processors decode an encoded pixel block as a pixel block having the first coverage type based on the control indicator for the pixel block indicating the first coverage type.

11. The apparatus of claim 10 , wherein the one or more processors decode an encoded pixel block determined to be a block having the first coverage type by accessing the mask corresponding to the pixel block.

12. The apparatus of claim 10 , wherein the one or more processors decode an encoded pixel block as a block having the second coverage type based on the control indicator for the pixel block indicating the second coverage type, and decode an encoded pixel block as a block having the third coverage type based on the control indicator for the pixel block indicating the third coverage type.

13. The apparatus of claim 1 , wherein the one or more processors further divide the mega encoded pixel block based on the multi-sample anti-aliasing case being implemented.

14. A method to facilitate pixel compression comprising:
converting an image to a plurality of pixels;
encoding the plurality of pixels, including:
dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks;
determining coverage information indicating a pixel span for pixels in each of the plurality of pixel blocks; and
encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded block;

transmitting the mega encoded pixel block for depth checking via an interface based on a multi-sample anti-aliasing case being implemented; and
transmitting the coverage information via the interface.

15. The method of claim 14 , further comprising:
generating a first encoded control indicator upon a determination that the pixel block has a first coverage type; and
generating a mask including the coverage information of each pixel in the pixel block.

16. The method of claim 15 , further comprising:
generating a second encoded control packet upon a determination that the pixel block has a second coverage type; and
generating a third encoded control packet upon a determination that the pixel block has a third coverage type.

17. The method of claim 16 , further comprising transmitting the encoded mega pixel block as an encoded control packet including one or more encoded control indicators and a data packet including one or more masks including the coverage information for each of the plurality of pixel blocks in the mega pixel block.

18. The method of claim 17 , wherein the encoded control packet is transmitted via a first bus and the data packet is transmitted via a second bus.

19. The method of claim 18 , further comprising decoding the encoded mega pixel block, including:
storing the one or more encoded control indicators and the data packet of the encoded mega pixel block; and
comparing each of the encoded pixel blocks to the stored encoded mega pixel block to determine coverage information for pixels in each of the encoded pixel blocks.

20. The method of claim 19 , wherein decoding the encoded mega pixel block further comprises decoding an encoded pixel block as a pixel block having the first coverage type based on the control indicator for the pixel block indicating the first coverage type, wherein the encoded pixel block having the first coverage type is decoded by accessing the mask corresponding to the pixel block.

21. The method of claim 20 , wherein decoding the encoded mega pixel block further comprises:
decoding an encoded pixel block as a pixel block having the second coverage type based on the control indicator for the pixel block indicating the second coverage type; and
decoding an encoded pixel block as a pixel block having the third coverage type based on the control indicator for the pixel block indicating the third coverage type.

22. At least one non-transitory computer readable medium having instructions, which when executed by one or more processors, cause the processors to:
convert an image to a plurality of pixels;
encode the plurality of pixels, including:
dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks;
determining coverage information indicating a pixel span for pixels in each of the plurality of pixel blocks; and
encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded block;

transmit the mega encoded pixel block for the depth checking via an interface based on a multi-sample anti-aliasing case being implemented; and
transmit the coverage information via the interface.

23. The computer readable medium of claim 22 , having instructions, which when executed by one or more processors, further causes the processors to:
generate a first encoded control indicator upon a determination that the pixel block has a first coverage type; and
generate a mask including the coverage information of each pixel in the pixel block.

24. The computer readable medium of claim 23 , having instructions,

Assignees

• Intel Corp

Inventors

• Maiyuran Subramaniam
• Garcia Pabon Jorge
• Ranganathan Vasanth
• Mandal Saikat
• Szerszen Karol
• Cruz Camacho Luis
• Appu Abhishek R
• Ray Joydeep

Classifications

• G09G2360/06

  Use of more than one graphics processor to process data before displaying to one or more screens · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T9/00

  Image coding (bandwidth or redundancy reduction for static pictures H04N1/41; coding or decoding of static colour picture signals H04N1/64; methods or arrangements for coding, decoding, compressing or decompressing digital video signals H04N19/00) · CPC title

• G06T15/40

  Hidden part removal · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title