Correcting power loss in NAND memory devices

Patent metadata

Field	Value
Publication number	US-10430116-B2
Application number	US-201715693121-A
Country	US
Kind code	B2
Filing date	Aug 31, 2017
Priority date	Aug 31, 2017
Publication date	Oct 1, 2019
Grant date	Oct 1, 2019

Abstract

Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.

First claim

The invention claimed is:

1. A method of managing a NAND flash memory comprising a number of physical pages, comprising:
detecting a power loss indicator at the NAND flash memory;
identifying a last-written physical page;
determining that the last-written physical page comprises more than a threshold number of low-read-margin cells; and
after determining that the last-written physical page comprises more than the threshold number of low-read-margin cells, providing a programming voltage to a subset of cells of the last-written physical page, wherein the subset of cells comprises at least the low-read-margin cells.

2. The method of claim 1 , further comprising determining that a programming flag is set during an initialization of the NAND flash memory, the programming flag being set during the initialization indicating that a programming cycle was in progress during a power loss.

3. The method of claim 1 , further comprising identifying cells of the last-written physical page that are at a first logical level corresponding to a highest threshold voltage distribution, wherein determining that the last-written physical page comprises more than the threshold number of low-read-margin cells comprises determining that the cells of the last-written physical page that are at the first logical level comprise more than the threshold number of low-read-margin cells.

4. The method of claim 1 , further comprising identifying cells of the last-written physical page that are at a first logical level corresponding to a highest threshold voltage distribution, wherein providing the programming voltage to the subset of cells of the last-written physical page comprises providing the programming voltage only to the cells of the last-written physical page that are at the first logical level.

5. The method of claim 1 , further comprising identifying cells of the last-written physical page that are at a first logical level corresponding to a highest threshold voltage distribution, wherein providing the programming voltage to the subset of cells of the last-written physical page comprises providing the programming voltage only to low-read-margin cells that are part of the cells of the last-written physical page that are at the first logical level.

6. The method of claim 1 , wherein identifying the last-written physical page comprises determining a last-assigned logical page of a block, and wherein the last-written physical page comprises the last-assigned logical page.

7. The method of claim 1 , wherein the determining that the last-written physical page comprises more than a threshold number of low-read-margin cells comprises:
identifying cells of the last-written physical page that are at a first logical level corresponding to a highest threshold voltage distribution;
reading the last-written physical page with a first read level for the first logical level;
reading the last-written physical page with a second read level for the first logical level, wherein the second read level is higher than the first read level; and
determining that a number of bit errors from the reading at the second read level is higher than the number of bit errors from the reading at the first read level by more than a threshold number of bit errors.

8. The method of claim 1 , wherein providing the programming voltage to the subset of cells of the last-written physical page comprises:
identifying cells of the last-written physical page that are at a first logical level corresponding to a highest threshold voltage distribution;
providing an inhibit voltage to at a bit line corresponding to a first remaining cell of the last-written physical page that is not at the first logical level; and
providing the programming voltage to a word line corresponding to the last-written physical page.

9. The method of claim 1 , further comprising:
reading the last-written physical page with a second read level for a first logical level, wherein the first logical level corresponds to a highest threshold voltage distribution, and wherein the second read level is higher than a standard read level for the first logical level;
identifying cells of the last-written page that returned a bit error when read at the second read level and is at the first logical level;
providing an inhibit voltage to a bit line corresponding to a first remaining cell of the last-written physical page that is at the first logical level and did not return a bit error when read at the second read level; and
providing the programming voltage at a word line corresponding to the last-written physical page.

10. The method of claim 1 , wherein providing the programming voltage to at least the low-read-margin cells comprises providing a number of programming pulses to at least the low-read-margin cells, wherein the number of programming pulses is less than a number of programming pulses of a programming cycle for the NAND flash memory.

11. A NAND flash memory comprising:
a memory array comprising a number of physical pages, where each of the number of physical pages comprises a number of cells; and
a memory controller programmed to perform operations comprising:
detecting a power loss indicator;
identifying a last-written physical page;
determining that the last-written physical page comprises more than a threshold number of low-read-margin cells; and
after determining that the last-written physical page comprises more than the threshold number of low-read-margin cells, providing a programming voltage to a subset of cells of the last-written physical page, wherein the subset of cells comprises at least the low-read-margin cells.

12. The NAND flash memory of claim 11 , wherein the memory controller is further programmed to perform operations comprising determining that a programming flag is set during an initialization of the NAND flash memory, the programming flag being set during the initialization indicating that a programming cycle was in progress during a power loss.

13. The NAND flash memory of claim 11 , wherein the memory controller is further programmed to perform operations comprising identifying cells of the last-written physical page that are at a first logical level corresponding to a highest threshold voltage distribution; and wherein determining that the last-written physical page comprises more than the threshold number of low-read-margin cells comprises determining that the cells of the last-written physical page that are at the first logical level comprise more than the threshold number of low-read-margin cells.

14. The NAND flash memory of claim 11 , wherein the memory controller is further programmed to perform operations comprising identifying cells of the last-written physical page that are at a first logical level corresponding to a highest threshold voltage distribution; and wherein providing the programming voltage to the subset of cells of the last-written physical page comprises providing the programming voltage only to the cells of the last-written page that are at the first logical level.

15. The NAND flash memory of claim 11 , wherein the memory controller is further programmed to perform operations comprising identifying cells of the last-written physical page that are at a first logical level corresponding to a highest threshold voltage distribution, wherein providing the programming voltage to the subset of cells of the last-written physical page comprises providing the programming voltage only to low-read-margin cells that are part of the cells of the last-written physical page that are at the first logical level.

16. The NAND flash memory of claim

Assignees

• Micron Technology Inc

Inventors

• Miller Michael G
• Muchherla Kishore Kumar
• Singidi Harish
• Ratnam Sampath
• Padilla Jr Renato C
• Besinga Gary F
• Feeley Peter Sean

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C5/144

  Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title