Methods, test structures, and test systems for determining a surface characteristic of a chip facet

Patent metadata

Field	Value
Publication number	US-10429313-B2
Application number	US-201715427185-A
Country	US
Kind code	B2
Filing date	Feb 8, 2017
Priority date	Feb 8, 2017
Publication date	Oct 1, 2019
Grant date	Oct 1, 2019

Abstract

A test system for determining a surface characteristic of a chip facet includes an on-chip waveguide, a detector, and a processor. The on-chip waveguide is configured to direct test light towards the facet, where a portion of the test light is reflected and a portion of the test light is transmitted. The detector is configured to measure an amount of the reflected portion or the transmitted portion, and the processor is configured to determine a surface characteristic of the facet, such as a facet angle, a facet curvature, and/or a facet roughness, on the basis of the measured amount.

First claim

We claim:

1. A test system for determining a surface characteristic of a chip facet, the test system comprising:
a first chip having a facet, the first chip including a first waveguide configured to direct test light towards the facet;
a detector configured to measure an amount of a portion of the test light reflected by the facet or a portion of the test light transmitted by the facet; and
a processor configured to determine a surface characteristic of the facet on the basis of the measured amount;
wherein the first waveguide is configured to receive the reflected portion of the test light from the facet, wherein the first chip further includes a second waveguide, wherein the first waveguide and the second waveguide are coupled by a directional coupler or a multimode interference coupler, and wherein the detector is coupled to the second waveguide to measure the reflected portion of the test light.

2. The test system of claim 1 , wherein the first chip is disposed in a wafer.

3. The test system of claim 1 , wherein the surface characteristic is one of: a facet angle, a facet curvature, or a facet roughness.

4. The test system of claim 1 , wherein the first waveguide is configured to direct the test light towards the facet in a direction perpendicular to a top edge of the facet.

5. The test system of claim 1 , wherein the facet includes a lithographically defined feature near the first waveguide, and wherein the lithographically defined feature is configured to facilitate reflection of the reflected portion of the test light or to facilitate transmission of the transmitted portion of the test light.

6. The test system of claim 1 , wherein the first waveguide is disposed at a different height from a main face of the first chip than the second waveguide.

7. The test system of claim 1 , wherein the first waveguide forms a test arm of a Michelson interferometer, and wherein the second waveguide forms a reference arm of the Michelson interferometer.

8. The test system of claim 7 , wherein the first chip further includes a phase shifter and a mirror, wherein the second waveguide is configured to direct reference light towards the mirror, and wherein the phase shifter is configured to phase shift the reference light.

9. The test system of claim 7 , wherein the reference arm has an adjustable optical path length.

10. The test system of claim 9 , wherein the optical path length is thermally adjustable or is adjustable by adjusting a charge-carrier concentration in the reference arm.

11. The test system of claim 7 , wherein the detector is a balanced photodetector configured to measure the amount of the reflected portion of the test light as an interference pattern.

12. The test system of claim 4 , wherein the detector is an integrated photodetector included in the first chip.

13. The test system of claim 1 , wherein the facet is inclined, and wherein the first waveguide includes a grating structure configured to diffract the test light such that the test light is directed towards the facet in a direction substantially perpendicular to the inclined facet.

14. The test system of claim 1 wherein the facet is defined at an edge of the first chip or as a sidewall of a trench.

15. A test system for determining a surface characteristic of a chip facet, the test system comprising:
a first chip comprising:
a facet, and
a first waveguide configured to direct test light towards the facet at an oblique first angle to a top edge of the facet;

a second chip disposed across a dicing lane from the first chip on a same wafer as the first chip;
a detector configured to measure a transmitted portion of the test light transmitted by the facet; and
a processor configured to determine a surface characteristic of the facet on the basis of the transmitted portion;

wherein the detector is an integrated photodetector included in the second chip, wherein the detector is configured to receive the transmitted portion of the test light and to measure the amount of the transmitted portion of the test light.

16. A test system for determining a surface characteristic of a chip facet, the test system comprising:
a first chip comprising a facet and a first waveguide configured to direct test light towards the facet;
a detector configured to measure a reflected portion of the test light reflected by the facet;
a processor configured to determine a surface characteristic of the facet on the basis of the reflected portion measured by the detector; and
wherein the first chip further comprises a second waveguide configured to receive the reflected portion of the test light from the facet, wherein the first waveguide is configured to direct the test light towards the facet at an oblique first angle to a top edge of the facet, and wherein the detector is configured to measure the reflected portion of the test light received from the second waveguide; and,
wherein the first waveguide includes an output segment disposed at the first angle to the top edge, wherein the second waveguide includes an input segment disposed at a second angle to the top edge, and wherein the first angle and the second angle are substantially equal in magnitude.

Assignees

• Elenion Tech Llc

Inventors

• Streshinsky Matthew Akio
• Novack Ari
• Hochberg Michael J

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/27

  Structural arrangements therefor · CPC title

• G01B11/30 Primary

  for measuring roughness or irregularity of surfaces · CPC title

• G01N21/8806 Primary

  Specially adapted optical and illumination features · CPC title

• G01R31/311

  of integrated circuits {(G01R31/31728 takes precedence)} · CPC title