Balanced unilateral frequency quadrupler

Patent metadata

Field	Value
Publication number	US-10425040-B2
Application number	US-201515507555-A
Country	US
Kind code	B2
Filing date	Aug 28, 2015
Priority date	Aug 29, 2014
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

An integrated frequency quadruplet consists of a pair of balanced frequency doublers that are driven in phase quadrature using a hybrid coupler. This approach results, effectively, in a “unilateral” multiplier that presents a match to the input-driving source, irrespective of the impedance of the doubler stages. The present invention applies this architecture to implement an integrated frequency quadruplet with output frequency of 160 GHz using quasi vertical GaAs varactors fabricated on thin silicon support membranes. The quadruplet has a balanced circuit architecture that addresses degradation issues often arising from impedance mis-matches between multiplier stages. A unique quasi-vertical diode process is used to implement the quadruplet, resulting in an integrated drop-in chip module that incorporates 18 varactors, matching networks and beamleads for mounting. The chip is tailored to fit a multiplier waveguide housing resulting in high reproducibility and consistency in manufacture and performance.

First claim

What is claimed is:

1. A frequency multiplier comprising:
an input for receiving an input signal of a fundamental frequency;
a pair of balanced frequency doublers each having an output node;
a second-stage balanced doubler including anti-series connected diodes, the second-stage balanced doubler bridging the output nodes of the pair of balanced frequency doublers;
and
a quadrature hybrid connected to the input for driving the pair of balanced frequency doublers in phase quadrature so that the pair of balanced frequency doublers each have an output signal, the two output signals being at twice the fundamental frequency and out of phase and which are used to drive the second-stage balanced doubler thus producing a single output signal at a frequency four times the input signal.

2. The frequency quadrupler of claim 1 , wherein the pair of balanced frequency doublers each comprise a pair of quasi-vertical GaAs varactors joined together in anti-series.

3. The frequency quadrupler of claim 1 , wherein each one of the pair of frequency doublers is identical.

4. The frequency quadrupler of claim 1 , wherein the output signal of the second-stage balanced doubler is a fourth-order harmonic.

5. A frequency quadrupler comprising:
a first input for receiving an input signal of a fundamental frequency;
a first pair of balanced frequency doublers each having an output node;
a first second-stage balanced doubler including anti-series connected diodes, the second-stage balanced doubler bridging the output nodes of the pair of frequency doublers;
a first quadrature hybrid connected to the first input for driving the first pair of balanced frequency doublers in phase quadrature so that the first pair of balanced frequency doublers each have an output signal, the two output signals being twice the fundamental frequency and out of phase and which are used to drive the first second-stage balanced doubler thus producing a single output signal at a frequency four times the input signal;
a second input for receiving the output signal from the first second-stage balanced doubler;
a second pair of balanced frequency doublers each having an output node;
a second second-stage balanced doubler including anti-series connected diodes, the second-stage balanced doubler bridging the output nodes of the pair of frequency doublers;
and
a second quadrature hybrid connected to the second input for driving the second pair of balanced frequency doublers in phase quadrature so that the second pair of balanced frequency doublers each have an output signal, the two output signals being twice the fundamental frequency and out of phase and which are used to drive the second second-stage balanced doubler thus producing a single output signal at a frequency 16 times the first input signal.

6. The frequency quadrupler of claim 5 ,
wherein the four balanced frequency doublers each comprise a pair of quasi-vertical GaAs varactors joined in anti-series.

7. The frequency quadrupler of claim 5 , wherein each one of the first and second pairs of frequency doublers is identical.

8. The frequency quadrupler of claim 5 , wherein the first and second quadrature hybrids respectively feeds the first and second pairs of frequency doublers in phase quadrature.

9. The frequency quadrupler of claim 5 , wherein the output signal of the first second-stage balanced doubler is a fourth-order harmonic and the output signal of the second second-stage balanced doubler is a fourth-order harmonic.

Assignees

• Univ Virginia
• Univ Virginia Patent Foundation

Inventors

• Alijabbari Naser
• Weikle Ii Robert M
• Bauwens Matthew

Classifications

• H03B19/18 Primary

  and elements comprising distributed inductance and capacitance · CPC title

• G06F7/68

  using pulse rate multipliers or dividers {pulse rate multipliers or dividers per se}(G06F7/70 takes precedence {; frequency division in electronic watches G04G3/02; frequency multiplication or division in oscillators H03B19/00; frequency dividing counters per se H03K23/00 - H03K29/00}) · CPC title

• H03B2200/0078

  generating or using signals in quadrature · CPC title

• H03D7/166

  using two or more quadrature frequency translation stages · CPC title