Programmable frequency selective surfaces

Patent metadata

Field	Value
Publication number	US-10424679-B2
Application number	US-201615289900-A
Country	US
Kind code	B2
Filing date	Oct 10, 2016
Priority date	Oct 10, 2016
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

A controllable frequency selective surface. The frequency selective surface has a plurality of conductive patches with integrated circuits straddling gaps between, and connected to, pairs of patches separated by gaps. Each integrated circuit presents a controllable impedance and as a result the characteristics of the frequency selective surface are controllable.

First claim

What is claimed is:

1. A controllable frequency-selective surface, comprising:
a dielectric substrate;
a plurality of conductive patches on a first surface of the dielectric substrate; and
a plurality of integrated circuits, each
straddling a gap between a first patch of the plurality of conductive patches and a second patch of the plurality of conductive patches,
connected at a first contact to the first patch and at a second contact to the second patch, and
being configured to receive a digital control word and to change, in response, an impedance between the first contact and the second contact, to cause an electromagnetic transmission or reflection characteristics of the frequency-selective surface to change.

2. The controllable frequency-selective surface of claim 1 , wherein each of the plurality of integrated circuits is configured to receive the digital control word through a conductive electrical data connection.

3. The controllable frequency-selective surface of claim 2 , further comprising:
a dielectric layer on the plurality of conductive patches; and
a conductive trace on the dielectric layer,
wherein the data connection comprises the conductive trace.

4. The controllable frequency-selective surface of claim 2 , wherein an integrated circuit of the plurality of integrated circuits straddles a first gap and comprises an array of switches configured to operate in a first state and in a second state, wherein a conductance across the first gap through the integrated circuit in the first state is different from the conductance across the first gap through the integrated circuit in the second state.

5. The controllable frequency-selective surface of claim 2 , wherein an integrated circuit of the plurality of integrated circuits straddles a first gap and comprises an array of switches configured to operate in a first state and in a second state, wherein a real part of a conductance across the first gap through the integrated circuit in the first state is different from the real part of the conductance across the first gap through the integrated circuit in the second state.

6. The controllable frequency-selective surface of claim 2 , wherein an integrated circuit of the plurality of integrated circuits straddles a first gap and comprises an array of switches configured to operate in a first state and in a second state, wherein an imaginary part of a conductance across the first gap through the integrated circuit in the first state is different from the imaginary part of the conductance across the first gap through the integrated circuit in the second state.

7. The controllable frequency-selective surface of claim 2 , wherein the integrated circuits of the plurality of integrated circuits are configured to receive the control word simultaneously.

8. The controllable frequency-selective surface of claim 7 , wherein:
an integrated circuit of the plurality of integrated circuits comprises an array of switches,
a conductance across the gap through the integrated circuit is determined by respective states of the switches of the array of switches, and
the integrated circuit is configured to set the states of the switches of the array of switches based on a received code word.

9. The controllable frequency-selective surface of claim 2 , wherein an integrated circuit of the plurality of integrated circuits comprises:
a shift register having:
a serial input connected to a control input of the integrated circuit and
a parallel output;

a decoder having:
an input connected to the parallel output of the shift register and
a parallel output comprising a plurality of switch control lines; and

an array of switches, each of the array of switches being connected to a respective switch control line of the plurality of switch control lines.

10. The controllable frequency-selective surface of claim 2 , wherein each switch is a transistor.

11. The controllable frequency-selective surface of claim 1 , wherein each of the plurality of integrated circuits is configured to receive the digital control word through an optical data connection.

12. The controllable frequency-selective surface of claim 11 , wherein an integrated circuit of the plurality of integrated circuits straddles a first gap and comprises an array of switches configured to operate in a first state and in a second state, wherein a conductance across the first gap through the integrated circuit in the first state is different from the conductance across the first gap through the integrated circuit in the second state.

13. The controllable frequency-selective surface of claim 11 , wherein an integrated circuit of the plurality of integrated circuits straddles a first gap and comprises an array of switches configured to operate in a first state and in a second state, wherein a real part of a conductance across the first gap through the integrated circuit in the first state is different from the real part of the conductance across the first gap through the integrated circuit in the second state.

14. The controllable frequency-selective surface of claim 11 , wherein an integrated circuit of the plurality of integrated circuits straddles a first gap and comprises an array of switches configured to operate in a first state and in a second state, wherein an imaginary part of a conductance across the first gap through the integrated circuit in the first state is different from the imaginary part of the conductance across the first gap through the integrated circuit in the second state.

15. The controllable frequency-selective surface of claim 11 , wherein the integrated circuits of the plurality of integrated circuits are configured to receive the control word simultaneously.

16. The controllable frequency-selective surface of claim 15 , wherein:
an integrated circuit of the plurality of integrated circuits comprises an array of switches,
a conductance across the gap through the integrated circuit is determined by respective states of the switches of the array of switches, and
the integrated circuit is configured to set the states of the switches of the array of switches based on a received code word.

17. The controllable frequency-selective surface of claim 11 , wherein an integrated circuit of the plurality of integrated circuits comprises:
a shift register having:
a serial input connected to a control input of the integrated circuit and
a parallel output;

a decoder having:
an input connected to the parallel output of the shift register and
a parallel output comprising a plurality of switch control lines; and

an array of switches, each of the array of switches being connected to a respective switch control line of the plurality of switch control lines.

18. The controllable frequency-selective surface of claim 11 , wherein each switch is a transistor.

19. The controllable frequency-selective surface of claim 11 , wherein the integrated circuit is configured to receive operating power in the form of illumination by light.

20. The controllable frequency-selective surface of claim 11 , wherein the optical data connection comprises a first solar cell, and
wherein the integrated circuit is configured to receive:
operating power through a second solar cell; and
a clock signal through a third solar cell,

the first solar cell being sensitive to light at a first wavelength, insensitive to light at a second wavelength, and insensitive to light at a third wavelength;
the first wavelength being different from the second wavelength and from

Assignees

• Raytheon Co

Inventors

• Frazier Gary A

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W44/259

  Optical signal interface · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H01Q15/002

  said selective devices being reconfigurable or tunable, e.g. using switches or diodes · CPC title